3D Stacked IC Pit Depth Compensation for Planarization
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Solution Overview
Problem
The integration of stacked multiple planes of memory cells with peripheral circuits in three-dimensional memory devices is challenging due to process variations in etching and deposition, which can result in inconsistent thicknesses of active and insulating layers, potentially damaging critical elements during planarization and affecting the uniformity and performance of memory cells.
Innovation Solution
A method involving the formation of a pit in a substrate with a stack of active layers alternating with insulating layers, where a specific insulating layer is deposited to ensure the sum of its thickness and the thicknesses of other layers matches the pit depth, with adjustments to compensate for process variations, and a planarization process is applied to protect the uppermost active layers and maintain the stack's height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed thickness is used for insulating layers in the stack, then the manufacturing process is simpler, but process variations cause the stack height to deviate from the target depth, potentially damaging critical elements during planarization
Solution Approach 1:
The patent changes the thickness parameter of insulating layers based on measured pit depth variations. Instead of using a fixed thickness for all insulating layers, the thickness is adjusted according to the actual pit depth in each region, compensating for etching process variations and ensuring the stack height matches the target depth
Solution Approach 2:
The patent implements a feedback mechanism where the actual pit depth is measured after etching, and this measurement is used to determine the thickness of insulating layers to be deposited. The insulating layer thickness is set based on the difference between target depth and measured depth, creating a closed-loop control system that compensates for process variations
2Reliability
If the stack height is increased to compensate for deep pits, then coverage is improved, but critical elements such as uppermost active layers are damaged during planarization
Solution Approach 1:
The patent applies different insulating layer thicknesses to different regions based on local pit depth requirements. Regions with deeper pits receive thicker insulating layers, while regions with shallower pits receive thinner layers, ensuring each region gets the exact coverage needed without over-compensating and damaging critical elements
Solution Approach 2:
The patent measures the pit depth before depositing insulating layers and calculates the required thickness in advance. This preliminary measurement and calculation ensure that the insulating layers are deposited with the precise thickness needed to reach the target depth without exceeding it, preventing damage to uppermost active layers during planarization
3Productivity
If process variations are not compensated, then the manufacturing process is faster, but the uniformity and performance of memory cells are affected
Solution Approach 1:
The patent adjusts the thickness parameter of insulating layers to compensate for process variations in pit etching. By changing the insulating layer thickness based on measured pit depth, the patent maintains consistent stack height and memory cell uniformity without requiring excessive process margins that would slow down manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the integration of memory cells with peripheral circuits while maintaining the stack's height and protecting critical elements, enhancing the uniformity and performance of memory cells by ensuring the active layers' critical thickness features are identical or close to identical, thus improving the overall manufacturing process.
Implementation Method 1
etching a substrate to form a pit
Implementation Method 2
depositing a stack of active layers alternating with insulating layers on the substrate
Implementation Method 3
applying a planarizing process to provide a planarized surface
Data Source
AI summary
An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.