3D Stacked Processor Power Mode Control
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Solution Overview
Problem
As the number of processors on a chip increases, on-chip communication between processors becomes problematic due to longer horizontal wiring, leading to cycle delays and the need for high-powered drivers, which worsen with increasing operating frequency.
Innovation Solution
The implementation of 3-D stacked multiprocessor devices, where processors are connected in a stacked configuration with shared input/output ports and a mode control circuit to operate in various power and frequency modes, reducing communication delays and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processors per chip is increased to accommodate more processors, then processing capacity is improved, but communication cycle delay increases and power consumption increases
Solution Approach 1:
The patent transitions from a 2D processor layout to a 3D stacked architecture, where processors are arranged in multiple vertical layers. This dimensional change allows processors to be positioned closer together in three-dimensional space, significantly reducing the physical distance for inter-processor communication and thereby decreasing communication cycle delays while maintaining high processing capacity.
Solution Approach 2:
The patent divides the processor system into multiple independent processor chips that are stacked vertically. Each processor chip can be independently fabricated and tested, then combined into a 3D stack. This segmentation allows for modular design, reduced individual chip complexity, and improved communication efficiency between processors in different layers.
2Productivity
If the number of processors per chip is increased to accommodate more processors, then processing capacity is improved, but high-powered drivers are required along communication paths
Solution Approach 1:
By stacking processors in three dimensions, the communication paths become shorter and more direct. The vertical stacking reduces the horizontal distance that signals must travel, allowing for lower-powered drivers while maintaining communication integrity across the processor array.
Solution Approach 2:
The patent introduces intermediate communication structures and control circuits that facilitate efficient data transfer between processors. These intermediary elements optimize signal transmission, reducing the power burden on individual drivers while maintaining high-speed communication across the multi-processor system.
3Speed
If the operating frequency is increased to improve performance, then processing speed is improved, but communication cycle delay increases
Solution Approach 1:
The 3D stacked architecture fundamentally reduces the physical communication distance between processors, allowing higher operating frequencies to be achieved without proportionally increasing communication delays. The shortened inter-processor paths enable faster signal transmission even at elevated frequencies.
4Loss of time
If 3D stacked processor chips are used to reduce communication delays, then communication efficiency is improved, but device complexity increases
Solution Approach 1:
The system is divided into separate processor chips that can be independently manufactured, tested, and assembled. Each chip is a discrete unit with standardized interfaces, making the overall system more manageable despite the 3D stacking complexity. This modular approach simplifies fabrication and assembly processes.
Solution Approach 2:
The patent employs universal interconnection interfaces and standardized bonding procedures that work across different processor chip configurations. This universality simplifies the integration process for 3D stacking, reducing the complexity burden despite the advanced architecture.
Data Source
AI summary
Processor devices are provided which operate in one of multiple power operating modes. A processor device comprises first and second processor chips connected in a stacked configuration, and which respectively include first and second processors that operate as a single logical processor. A mode control circuit generates control signals and different sets of configuration parameters. A first control signal is generated to input a first set of configuration parameters to the single logical processor, which is utilized to operate the single logical processor in a first power operating mode wherein the first processor is turned on and the second processor is turned off. A second control signal is generated to input a second set of configuration parameters to the single logical processor, which is utilized to operate the single logical processor in a second power operating mode wherein both the first processor and the second processor are turned on.