3D Stacked Switching Voltage Regulator for Lower Switching Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Switching voltage regulators face challenges in reducing switching loss, which affects their conversion efficiency.
Innovation Solution
The design incorporates a converting circuit with at least one switch on a first die and a blocking transistor on a second die, both vertically stacked, and operates at different switching frequencies to minimize switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If switching operation is performed to generate output voltage, then voltage conversion function is achieved, but switching loss increases reducing conversion efficiency
Solution Approach 1:
The patent divides the switching circuit into multiple independent switches (first switch, second switch, third switch, fourth switch) distributed across different dies. Each switch operates independently with optimized characteristics, allowing the system to segment the switching loss across multiple components rather than concentrating it in a single switch, thereby reducing overall switching loss while maintaining conversion efficiency.
Solution Approach 2:
The patent transitions from a planar single-die architecture to a three-dimensional stacked multi-die architecture. By vertically stacking multiple dies containing different switches and transistors, the patent creates a new spatial dimension for circuit organization. This 3D configuration reduces parasitic inductance and enables shorter current paths, which directly reduces switching loss and improves conversion efficiency.
2Device complexity
If multiple switches are integrated on a single die, then device complexity is reduced, but switching loss increases due to larger parasitic inductance
Solution Approach 1:
Instead of integrating all switches on a single die, the patent segments the switching circuit across multiple dies. Each die contains specific switches and transistors optimized for their function, reducing the parasitic inductance within each die while maintaining overall circuit functionality. This segmentation resolves the contradiction by distributing complexity across multiple simpler units.
Solution Approach 2:
The patent uses vertical stacking to connect switches across different dies through inter-die vias, creating short current paths in the vertical dimension. This 3D interconnection approach reduces the horizontal current path length and associated parasitic inductance, thereby reducing switching loss while keeping each individual die relatively simple in structure.
3Speed
If switching frequency is increased to improve response speed, then voltage regulation performance is improved, but switching loss increases
Solution Approach 1:
The patent divides the switching operation across multiple switches that can operate at different frequencies or phases. This segmentation allows the system to achieve fast response through coordinated switching while distributing the switching loss across multiple components, mitigating the penalty of high-frequency operation.
Solution Approach 2:
The 3D stacked architecture reduces parasitic inductance and enables faster switching transitions by shortening current paths. This structural optimization allows the circuit to operate at higher frequencies with reduced switching loss, as the reduced parasitics minimize the energy lost during each switching transition.
Data Source
AI summary
Provided is a switching voltage regulator including: a converting circuit configured to receive an input voltage and to generate an output voltage through a switching operation; and a control circuit configured to cause the output voltage to be generated by controlling the switching operation, wherein the converting circuit includes: at least one switch formed on a first die and configured to perform the switching operation under control of the control circuit; and at least one blocking transistor formed on a second die and electrically connected to at least one first transistor, and wherein the first die is vertically stacked on the second die.