3D Stacked sASIC Platform via TSV Interconnects
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Solution Overview
Problem
The increasing complexity and cost of fabricating highly complex application-specific integrated circuits (ASICs) have driven a need for new approaches to three-dimensional integration that offer cost reductions and other advantages of standardized base arrays combined with programmable building blocks, while maintaining or improving performance and reducing power consumption.
Innovation Solution
A 3D stacked structured ASIC (sASIC) platform is developed, featuring multiple 2D reconfigurable sASIC levels interconnected through hard-wired arrays of 3D vias, specifically through-silicon vias (TSVs), which facilitate high-density integration and low-energy, high-speed photonic links, enabling a device that is more dense and reconfigurable than custom ASICs while being faster and more economical to fabricate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional fabrication techniques are used to improve performance and reduce power consumption, then device density and functionality are improved, but fabrication duration and costs increase
Solution Approach 1:
The fabrication process is segmented into two distinct phases: (1) parallel fabrication of multiple sASIC die levels using standardized base arrays, and (2) post-fabrication customization through mask-programmed vias and 3D stacking. This segmentation allows the majority of the device to be fabricated efficiently in bulk, while customization is applied only where needed, reducing overall fabrication time while maintaining high device density.
Solution Approach 2:
The sASIC base arrays are pre-fabricated with standardized logic blocks, interconnects, and via structures before customization. This preliminary action enables wafer-level parallel fabrication of multiple die levels, significantly reducing fabrication duration compared to fully custom ASIC processes, while still achieving high device density through subsequent 3D stacking.
2Productivity
If three-dimensional fabrication techniques are used to improve performance and reduce power consumption, then device density and functionality are improved, but fabrication costs increase
Solution Approach 1:
A universal sASIC base array platform is used across multiple die levels, with standardized logic blocks, interconnect architectures, and via structures. This universality allows wafer-level parallel fabrication and re-use of the same fabrication masks and processes across all levels, significantly reducing NRE costs and per-device fabrication costs while enabling high device density through 3D stacking.
Solution Approach 2:
The standardized sASIC base array platform serves as a reusable template that can be fabricated once at wafer level and then customized for multiple different applications through mask-programmed vias. This approach recovers the high NRE costs of custom ASIC fabrication by allowing the same base structure to be reused across numerous devices, reducing per-unit cost while maintaining high device density.
3Ease of manufacture
If standardized base arrays are used to reduce NRE costs, then fabrication economy is improved, but reconfigurability and adaptability are reduced
Solution Approach 1:
The sASIC base array includes dynamically configurable elements such as mask-programmed via layers and reconfigurable interconnect structures that allow the device to be adapted to different applications after fabrication. This dynamic configurability maintains reconfigurability and adaptability while using standardized base arrays for cost-effective fabrication.
Solution Approach 2:
The mask-programmed via layers enable post-fabrication customization of the interconnect architecture without requiring additional fabrication steps. The device essentially configures itself through the programming of via patterns, maintaining full adaptability and reconfigurability while using economical standardized base array fabrication processes.
4Speed
If custom ASICs are used to achieve high performance, then speed and power efficiency are improved, but fabrication complexity and cost increase
Solution Approach 1:
The device is segmented into a standardized sASIC base array portion and a customized via-interconnect portion. This segmentation allows the majority of the device structure to be fabricated using simple, reusable processes, while only the interconnect layer requires custom fabrication steps, significantly reducing overall fabrication complexity while maintaining high device speed and performance.
Data Source
AI summary
A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.