3D Stacked Semiconductor Structure With Division Contacts for Reliability
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating a solution for high integration density and improved reliability.
Innovation Solution
A three-dimensional semiconductor device design featuring vertically stacked transistors with a division structure that includes a division liner pattern and connection metal pattern, along with a substrate and insulating pattern configuration, to enhance integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size and reduced design rule, then the pattern size and design rule are reduced, but the operational properties of the semiconductor device deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked transistors. Multiple active regions (first active region, second active region, third active region) are stacked vertically on the substrate, allowing multiple transistor channels to occupy the same footprint area. This vertical stacking increases integration density while maintaining adequate transistor dimensions for reliable operation, thus resolving the contradiction between small pattern size and operational properties.
Solution Approach 2:
The patent divides the semiconductor device into multiple segmented active regions stacked vertically. Each active region contains separate source/drain patterns and channel patterns, with division structures (including division liner patterns and connection metal patterns) separating and connecting them. This segmentation allows independent optimization of each transistor layer while achieving high integration density through vertical stacking.
2Area of moving object
If vertically stacked transistors are implemented to increase integration density, then the physical area per logic cell is reduced, but the device complexity increases
Solution Approach 1:
The device is segmented into multiple standardized active regions (first, second, third active regions) with repeating structural elements. Each active region contains source/drain patterns, channel patterns, and gate electrodes that can be replicated vertically. This modular segmentation simplifies the fabrication process despite the three-dimensional structure, as the same patterns are repeated across multiple layers.
Solution Approach 2:
The gate electrode structure serves multiple functions: it controls the channel in each active region it contacts and provides electrical connection between stacked active regions. The division structures serve dual purposes of separating adjacent active regions laterally and providing vertical electrical connections through the stack, reducing the need for additional dedicated connection structures.
3Reliability
If division structures with connection metal patterns are added to connect stacked active regions, then the electrical connectivity between source/drain patterns is improved, but the manufacturing complexity increases
Solution Approach 1:
The division structure merges multiple functions into a single integrated component: it provides lateral separation between adjacent active regions through the division liner pattern, provides vertical electrical connection through the connection metal pattern, and serves as an etch stop and structural support. This consolidation reduces the total number of separate manufacturing steps compared to implementing separate separation and connection structures.
Solution Approach 2:
The connection metal pattern acts as an intermediary structure that bridges the source/drain patterns of vertically stacked active regions. It provides a controlled impedance path for electrical signals between layers while being integrated into the division structure, simplifying the overall interconnection architecture compared to using separate via and interconnect structures.
Data Source
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AI summary
A three-dimensional semiconductor device may include a first active region, which includes a first channel pattern and a first source/drain pattern connected to each other, on a substrate, a second active region, which includes a second channel pattern and a second source/drain pattern connected to each other, on the first active region, a gate electrode on the first and second channel patterns, a bottom active contact electrically connected to the first source/drain pattern and extended from the first source/drain pattern in a first direction, a lower metal layer provided below the bottom active contact, the lower metal layer including bottom via patterns and bottom interconnection lines electrically connected to the bottom active contact, and a division structure electrically connected to at least one of the bottom via patterns. The division structure may include a division liner pattern and a connection metal pattern penetrating the same.