3D Stacked Semiconductor Device With Through Silicon Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The development of true three-dimensional integrated circuits (3DICs) faces challenges in yield and reliability due to complex architectures and deep submicron process generation difficulties, with existing testing techniques being inadequate for these complex systems.
Innovation Solution
The implementation of a semiconductor device with multiple mono-crystallized semiconductor layers stacked using Through Silicon Via technology, incorporating programmable interconnect tiles and antifuse-based programming circuitry in an 'Attic' layer above the functional circuitry, enabling flexible configuration and redundancy for improved yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If Through Silicon Via technology is used to stack multiple mono-crystallized semiconductor layers, then device complexity and integration density are improved, but yield and reliability deteriorate due to manufacturing difficulties in deep submicron process generations
Solution Approach 1:
The patent transitions from planar 2D IC architecture to three-dimensional stacked architecture by vertically stacking multiple mono-crystallized semiconductor layers using Through Silicon Via technology. This dimensional change increases integration density by utilizing the vertical space above each logic element, allowing multiple functional layers to be integrated in a compact footprint while maintaining electrical connectivity through vertical vias.
Solution Approach 2:
The patent divides the semiconductor device into multiple discrete mono-crystallized layers, each containing specific functional elements such as logic elements, memory elements, or interconnect structures. This segmentation allows independent fabrication and testing of individual layers before stacking, improving yield by isolating defects to specific layers and enabling replacement of defective layers without scrapping the entire device.
2Adaptability or versatility
If complex 3D IC architectures are constructed with multiple stacked layers, then functionality and integration are improved, but testing and repair become more difficult
Solution Approach 1:
The patent incorporates test structures, redundancy elements, and repair circuitry during the fabrication process rather than adding them later. Test vias and redundancy logic are built into the stacked architecture from the beginning, allowing for automated testing and repair operations without requiring complex external equipment or disassembly of the device.
Solution Approach 2:
The patent implements self-test and self-repair capabilities within the 3D IC architecture through integrated test logic and redundancy mechanisms. The device can automatically detect defects in its own structure and activate backup elements to maintain functionality, reducing the need for external testing equipment and simplifying the testing process.
Data Source
AI summary
A semiconductor device includes a first mono-crystallized semiconductor layer; and a second mono-crystallized semiconductor layer; wherein said first and second mono-crystallized semiconductor layers are overlaying one on top of the other, and wherein said first mono-crystallized semiconductor layer comprise repeating memory structure with sub structures defined by etching.