3D Stacked Semiconductor Device Using Multi-Etch Masks
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the volume of semiconductor elements while increasing circuit density, which is essential for meeting the trends of lightweight, thin, and small electronic products.
Innovation Solution
A 3D stacking semiconductor device is developed with interlaced conductive and insulating layers, utilizing a method that involves multiple etch masks to create landing areas and etched depths, forming interlayer connectors that connect corresponding conductive layers, thereby increasing circuit density within a fixed volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar semiconductor structures are used, then manufacturing process is simple, but circuit density and device performance are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) semiconductor structures to three-dimensional (3D) stacked structures by vertically stacking multiple active layers. This dimensional change enables significantly higher circuit density by utilizing the vertical space above the substrate, allowing multiple circuits to be stacked one on top of another while maintaining compact footprints.
Solution Approach 2:
The semiconductor device is divided into multiple discrete active layers stacked vertically, with each layer containing conductive layers, insulating layers, and functional regions. This segmentation allows independent design and optimization of each layer while achieving high overall density through vertical integration.
2Volume of moving object
If device volume is reduced for compact products, then portability improves, but manufacturing precision requirements increase
Solution Approach 1:
The etching process is divided into multiple sequential steps, with each step removing material to a specific depth and creating landing areas at different vertical positions. This segmented approach allows precise control over the three-dimensional structure formation, ensuring accurate alignment and connectivity between stacked layers while maintaining compact device volume.
3Quantity of substance
If multiple etch masks are used to create complex 3D structures, then circuit density increases, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct etching steps, each using a specific etch mask to create particular features at defined depths. This segmentation transforms a complex single-step process into manageable sequential steps, where each step builds upon the previous one to gradually form the final three-dimensional stacked structure with high circuit density.
Data Source
AI summary
A 3D stacking semiconductor device and a manufacturing method thereof are provided. The method includes using a set of N etch masks for creating O different numbers of removed layers in the conductive layers and the insulating layers for forming landing areas on the conductive layers in the contact region, each mask including mask and etch regions, N being an integer equal to or larger than 2, O being an integer larger than 2, 2N-1<O≤2N; and removing a portion of the conductive layers and the insulating layers to create etched depths extending from a surface layer to the corresponding landing areas on the conductive layers; wherein the etched depths of corresponding etching steps are 1P, 2P and nP layers of the stacking structures, n being an integer equal to or larger than 3, and P being an integer equal to or larger than 1.