3D Stacked Transistor Spacers to Limit S/D Epi Lateral Growth
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Solution Overview
Problem
The lateral epitaxial growth of source and drain regions in semiconductor manufacturing limits the reduction in spacing between adjacent semiconductor devices and interconnect contacts, hindering the miniaturization of integrated circuits.
Innovation Solution
The use of dielectric spacers on the inner and outer sidewalls of channel regions to inhibit lateral growth of source and drain regions during epitaxial growth, allowing for closer spacing of semiconductor devices and interconnect contacts without causing shorts, thereby enabling the reduction of overall integrated circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lateral epitaxial growth of source and drain regions is allowed, then complete formation of source and drain regions is achieved, but spacing between adjacent semiconductor devices and interconnect contacts must be large to prevent shorts
Solution Approach 1:
A dielectric spacer is introduced as an intermediary layer between adjacent semiconductor devices. This spacer physically separates the source and drain regions of neighboring devices during epitaxial growth, preventing lateral diffusion that would cause shorts while still allowing complete formation of the source and drain regions within each device.
Solution Approach 2:
The dielectric spacer is formed on the sidewalls of the channel region before the epitaxial growth of source and drain regions. This preliminary structure confines the lateral growth of dopants during subsequent thermal processing, ensuring that source and drain regions do not extend beyond the channel boundaries into adjacent devices.
2Area of stationary object
If spacing between adjacent semiconductor devices is reduced, then integrated circuit size is scaled down, but lateral epitaxial growth causes shorts between devices
Solution Approach 1:
The dielectric spacer serves as a protective intermediary that enables reduced device spacing. By confining lateral epitaxial growth, the spacer allows devices to be placed closer together without compromising reliability, thus enabling circuit scaling while maintaining short prevention.
Solution Approach 2:
The dielectric spacer provides localized confinement of epitaxial growth at the critical interfaces between adjacent devices. This local quality control ensures that source and drain regions maintain proper boundaries only where needed at device edges, while allowing full formation within each device region.
3Area of stationary object
If dielectric spacer is used to confine lateral growth, then spacing between devices can be reduced, but device structure complexity increases
Solution Approach 1:
The dielectric spacer divides the structure into distinct regions: the channel region, the spacer region, and the source/drain regions. This segmentation provides clear spatial boundaries that control epitaxial growth while maintaining a systematic and manufacturable structure through standard deposition and etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a reduction in the spacing between semiconductor devices and interconnect contacts, resulting in smaller integrated circuit sizes compared to traditional methods without dielectric spacers, while preventing electrical shorts.
Implementation Method 1
epitaxially growing source and drain regions for the lower transistor and the upper transistor of each of the first semiconductor device and the second semiconductor device. The first dielectric spacer and the second dielectric spacer inhibit lateral growth of the source and drain regions during the epitaxially growing of the source and drain regions.
Data Source
AI summary
An integrated circuit includes a first semiconductor device and a second semiconductor device adjacent to the first semiconductor device. Each of the first and second semiconductor devices includes a lower transistor and an upper transistor on the lower transistor, and the upper and lower transistors each include a source region, a drain region, and a channel region extending between the source region and the drain region. The integrated circuit also includes a first dielectric spacer extending along an inner sidewall of the channel region of the upper and/or lower transistor of the first semiconductor device, a second dielectric spacer facing the first dielectric spacer and extending along an inner sidewall of the channel region of the upper and/or lower transistor of the second semiconductor device. The integrated circuit also includes an interconnect contact between the first semiconductor device and the second semiconductor device.