3D Stacked SRAM Cell Layout With 2D Channels for Fast Data Access
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Solution Overview
Problem
The challenge in semiconductor devices, particularly static random-access memory (SRAM) devices, is to enhance integration and operational performance while maintaining fast operation speed and accuracy, as they occupy a significant portion of central processing units (CPUs) and require efficient communication with CPUs.
Innovation Solution
A monolithic three-dimensional stack structure for SRAM devices is implemented, comprising multiple tiers of transistors with channel layers made of two-dimensional semiconductor materials, and inter-tier connections through metal lines, allowing for improved electrical connectivity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar SRAM structure is used, then manufacturing process is simpler, but integration density and communication efficiency with CPU are insufficient
Solution Approach 1:
The patent transitions from conventional planar (2D) SRAM structure to a three-dimensional stacked architecture with multiple tiers (first tier, second tier, third tier) of transistors arranged vertically. This dimensional change enables significantly higher integration density by utilizing the vertical space, allowing more transistor components to be packed into a smaller footprint area, thereby resolving the contradiction between integration density and structural complexity.
Solution Approach 2:
The SRAM device is divided into multiple functional tiers, with each tier containing specific transistor components (e.g., first tier with first and second transistors, second tier with third and fourth transistors, third tier with fifth and sixth transistors). This segmentation allows for modular design and independent optimization of each tier while achieving high overall integration density through vertical stacking.
2Productivity
If transistor size is reduced for higher integration, then integration density improves, but maintaining fast operation speed and accuracy becomes more difficult
Solution Approach 1:
By stacking transistors in three dimensions rather than continuing to scale them down in two dimensions, the patent achieves higher integration density without proportionally increasing the lateral size of individual transistors. The vertical arrangement allows for reduced contact resistance and optimized signal paths that maintain fast operation speeds while increasing integration density.
Solution Approach 2:
The patent employs different gate configurations for different transistor tiers, with gates arranged in specific orientations (e.g., first gates extending in a first direction, second gates extending in a second direction). This local optimization of gate structures allows each tier to be tuned for its specific functional requirements, maintaining operational performance while achieving high integration density.
3Productivity
If multi-tier stacked structure is implemented, then integration density and data access capability improve, but manufacturing precision requirements increase
Solution Approach 1:
The device is segmented into distinct tiers with clearly defined interfaces and connection layers. Each tier can be manufactured and tested independently before integration, which reduces the overall manufacturing precision requirements compared to a monolithic structure. The segmented approach allows for better control of alignment between tiers through standardized interface designs.
Solution Approach 2:
Connection layers and interconnect structures serve as intermediaries between the different tiers, providing standardized interfaces that facilitate precise alignment and electrical connection. These intermediary structures simplify the manufacturing process by breaking down the complex alignment requirements into manageable steps through controlled impedance pathways and regulated voltage levels between tiers.
Data Source
AI summary
Provided are a static random-access memory (SRAM) device having a monolithic three-dimensional stack structure and an electronic apparatus including the SRAM device. The SRAM device includes a first tier including first and second transistors, a second tier stacked on the first tier and including third and fourth transistors, and a third tier stacked on the second tier and including fifth and sixth transistors. Each of the first to sixth transistors includes a channel layer including a two-dimensional semiconductor material. A gate of at least one of the fifth and sixth transistors is arranged to intersect a gate of at least one of the first to fourth transistors.