3D Stacked SRAM Shared Gate Cross-Couple Contact Design
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Solution Overview
Problem
The challenge in semiconductor technology is to enhance the areal density and performance of static random access memory (SRAM) cells while minimizing the physical space required, as planar-structured transistors face limitations in size reduction and density integration.
Innovation Solution
A 3D stacked SRAM device design is implemented, where transistors are vertically stacked with shared gates and cross-couple contacts, allowing for a more compact layout by using a method that includes providing metal gates, performing gate cutting, and filling recesses with dielectric material to create cross-couple contacts, thereby optimizing transistor placement and reducing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar-structured transistors are used in SRAM, then the device structure is simple and manufacturing is easier, but the areal density is low and chip size is large
Solution Approach 1:
The patent transitions from planar 2D transistor layout to 3D vertically stacked transistor architecture. Multiple transistor layers are stacked vertically with shared gates, enabling higher density integration without increasing the lateral chip footprint. This dimensional change allows more transistors to be packed into the same area by utilizing the vertical dimension.
Solution Approach 2:
The patent implements shared gates where a single gate structure controls multiple transistors across different layers. Specifically, first and second gates are shared between transistors in different layers, reducing the total number of gate structures needed and simplifying the overall device architecture while maintaining control functionality.
2Quantity of substance
If more transistors are integrated in a single plane, then the areal density increases, but the transistor size must be reduced which faces physical limits
Solution Approach 1:
The patent moves transistor integration from a single 2D plane to multiple vertical layers. By stacking transistors vertically and sharing gates between layers, the effective integration area is expanded into the third dimension, allowing higher transistor density without further reducing individual transistor dimensions in the lateral direction.
Solution Approach 2:
The shared gate structures serve multiple functions by controlling transistors in different layers simultaneously. A single gate structure performs the control function for multiple transistors, reducing the total component count and enabling higher density integration without proportionally increasing control circuit complexity.
3Area of moving object
If 3D stacked transistor structure is used, then the areal density and transistor integration are improved, but the device structure becomes more complex
Solution Approach 1:
The patent reduces structural complexity by merging gate functions across layers. Shared gates allow a single gate structure to control multiple transistors in different layers, reducing the total number of gate structures and interconnections needed compared to having separate gates for each transistor, thereby simplifying the overall 3D structure.
Solution Approach 2:
The shared gate structures provide multi-functional control, serving as the control element for multiple transistors across different layers. This universal control mechanism reduces the number of independent control structures required, simplifying the device architecture despite the vertical stacking complexity.
Data Source
AI summary
A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a static random access memory (SRAM) including a plurality of transistors disposed in a first layer and a second layer. The first layer includes a first shared gate of a first transistor and a second shared gate of a second transistor, among the plurality of transistors. The second layer is disposed above the first layer and includes a third shared gate of a third transistor and a fourth shared gate of a fourth transistor, among the plurality of transistors. The third shared gate is disposed above the first shared gate, and the fourth shared gate is disposed above the second shared gate. The SRAM further includes a first shared contact, a second shared contact, a first cross-couple contact connecting the fourth shared gate and the first shared contact, and a second cross-couple contact connecting the third shared gate and the second shared contact.