3D Stacked Thyristor Memory Cell Arrays
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Solution Overview
Problem
Conventional 1T1C DRAM technology faces challenges in scaling due to maintaining capacitance value and low transistor leakage, and alternative DRAM cells like PNPN thyristors have issues with data retention and process control, especially in small geometry cells.
Innovation Solution
The development of 3D stacked thyristor memory cell arrays with semiconductor pillars of alternating polarity, connected by parallel and intermediate conducting lines, allowing for the formation of multiple layers of memory cells with improved switching speed and reduced cell size, using epitaxially grown semiconductor materials and in-situ doped layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 1T1C DRAM technology is used for scaling, then manufacturing process is well-established, but capacitance value maintenance and transistor leakage become major problems
Solution Approach 1:
The patent transitions from conventional 2D planar DRAM cell structures to 3D vertically-stacked thyristor memory cells. This dimensional change enables higher density by stacking multiple memory cell layers vertically, with each layer containing thyristor cells formed by alternating polarity semiconductor layers (N-type and P-type) stacked to create the PNPN structure. The vertical stacking approach resolves the scaling limitations of 1T1C cells while maintaining manufacturability through epitaxial growth processes.
2Area of moving object
If PNPN thyristor cells are used to overcome scaling challenges, then cell size is reduced, but data retention issues arise in small geometry cells
Solution Approach 1:
The patent employs precise control of semiconductor layer parameters including doping concentrations, layer thicknesses, and material compositions during epitaxial growth. By optimizing these parameters, the thyristor cells achieve both small geometry dimensions and adequate data retention characteristics. The alternating N-type and P-type layers are grown with controlled doping profiles to ensure proper thyristor switching behavior and charge retention in the depleted regions.
Solution Approach 2:
The memory cell structure utilizes composite semiconductor materials with alternating polarity layers (N-type and P-type doped silicon or similar semiconductor materials). This composite structure creates the thyristor's four-layer PNPN configuration, enabling both compact cell size and reliable data retention through the inherent charge storage capabilities of the reverse-biased junctions in the stacked configuration.
3Ease of operation
If PNPN thyristors are operated in breakdown region for data writing, then data can be written into the cell, but process control and power consumption challenges increase
Solution Approach 1:
The patent controls the operating parameters of the thyristor cells to enable data writing through controlled breakdown operation. By precisely managing the voltage pulses applied to the cell and the doping profiles of the semiconductor layers, the system achieves reliable data writing while limiting excessive power consumption. The epitaxially-grown layers provide consistent breakdown characteristics that facilitate controlled operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances data retention and reduces cell size, addressing the scaling challenges of conventional DRAM technology while maintaining efficient process control and power consumption.
Implementation Method 1
The semiconductor pillars comprise epitaxially grown semiconductor materials with in-situ doped layers of alternating polarity
Data Source
AI summary
Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon pillars are epitaxially grown in-situ. Intermediate conducting lines formed in place of the removed nitride layer of the ONO stack contact the middle P-layer of silicon pillars. The silicon pillars form two arrays of thyristor memory cells, one stacked upon the other, having the intermediate conducting lines as common connections to both arrays. The stacked arrays can also be provided with assist-gates.