3D Stacked Chip Tile Mapping for Low-Latency Data Flow
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Solution Overview
Problem
Existing 3D stacked semiconductor devices face challenges in efficiently routing data channels and achieving high bandwidth due to inadequate Placer and Router solutions, leading to routing congestion and low bandwidth in inter-chip communication.
Innovation Solution
A method for forming a 3D stacked device by aligning semiconductor chips vertically, optimizing tile-to-tile and pin-to-pin connections to minimize latency and congestion, using a flowchart-based approach to assign tiles and pins to minimize bus and net delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing Placer and Router solutions are used in 3D stacked devices, then routing can be performed, but routing congestion and low bandwidth occur
Solution Approach 1:
The patent transitions from 2D routing to 3D stacked architecture, utilizing the vertical dimension to increase connectivity. Multiple semiconductor chips are stacked vertically with inter-chip connections, allowing data to flow through multiple layers simultaneously. This dimensional change enables significantly higher bandwidth (achieving 1 TBps aggregate bandwidth) by providing additional routing paths that are not available in planar 2D layouts.
Solution Approach 2:
The patent divides the computational workload and data routing into multiple independent channels across different chip layers. Instead of single congested paths, data is segmented into multiple parallel streams that can be routed through different vertical channels. This segmentation of data flow into multiple independent paths eliminates routing congestion by distributing traffic across the 3D architecture.
2Productivity
If more connections are added to increase bandwidth, then data transfer capacity increases, but routing complexity and congestion increase
Solution Approach 1:
By stacking chips vertically in the Z-dimension, the patent adds spatial dimensions for routing without increasing planar complexity. Multiple connections are established through vertical inter-chip pathways rather than competing for limited 2D substrate space. This enables achieving 1 TBps aggregate bandwidth with 26k/19k nets while maintaining manageable routing complexity through the use of vertical channels and standardized inter-chip interfaces.
3Adaptability or versatility
If vertical stacking is implemented to increase connectivity, then more data paths are available, but placement and routing difficulty increases
Solution Approach 1:
The patent performs tile assignment and connection optimization before final placement and routing. By pre-determining which tiles on different chips should be connected and optimizing these assignments to minimize bus delays, the complex placement and routing problems are solved in a systematic sequence. This preliminary optimization of tile-to-tile mappings simplifies the subsequent physical placement and routing steps.
Solution Approach 2:
The patent optimizes placement and routing by changing key parameters such as tile assignment configurations and connection mappings. By adjusting these parameters to minimize bus delays and optimize data flow paths, the patent achieves efficient vertical connectivity while managing placement and routing complexity through parameter optimization rather than brute-force approaches.
Data Source
AI summary
A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.