3D Stacked Transistor Interconnect Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties and challenges in achieving high performance and integration density.
Innovation Solution
A three-dimensional semiconductor device design with vertically stacked transistors, including a division structure that connects source/drain patterns through a division liner and connection metal pattern, reducing the occupied area and minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS-FETs are scaled down to increase integration density, then the number of transistors per unit area increases, but operational properties deteriorate and performance decreases
Solution Approach 1:
The patent transitions from two-dimensional planar transistor layouts to three-dimensional vertically stacked transistor structures. Multiple transistor channels are stacked vertically above each other, enabling higher integration density without further scaling the lateral dimensions of individual transistors. This vertical stacking maintains operational properties by preserving adequate channel dimensions while increasing the number of functional units per unit area.
Solution Approach 2:
The transistor structure is divided into multiple stacked channels with separate source and drain regions for each channel. Each channel can be independently controlled by gate electrodes, allowing segmented control of current flow through each vertical segment. This segmentation enables maintaining optimal channel dimensions for each transistor while achieving high integration through vertical stacking.
2Ease of manufacture
If traditional interconnection structures are used in three-dimensional devices, then manufacturing is simpler, but parasitic capacitance increases and reliability decreases
Solution Approach 1:
A division structure comprising a division liner pattern and connection metal pattern is introduced as an intermediary element between the bottom active contact and the lower metal layer. This division structure separates and isolates adjacent interconnection lines, reducing parasitic capacitance between them. The division liner acts as an insulating barrier while the connection metal pattern provides electrical connection, achieving both low parasitic capacitance and manufacturing feasibility.
3Quantity of substance
If vertically stacked transistors are implemented, then integration density increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Multiple transistor channels are merged into a single vertical stack structure, sharing common substrate regions and isolation structures. The gate electrodes for different channels are positioned at different vertical levels but can be formed using similar process steps. This merging approach achieves high integration density while managing complexity through structural consolidation and process standardization.
Solution Approach 2:
The patent resolves structural complexity by moving the differentiation between multiple transistors from the lateral plane to the vertical dimension. Instead of placing transistors side-by-side in two dimensions, they are stacked in three dimensions with clear vertical separation. This dimensional transition simplifies the lateral layout and reduces inter-transistor interference while maintaining manufacturability through adapted fabrication processes.
4Reliability
If division structures are added to reduce parasitic capacitance, then reliability improves, but manufacturing complexity increases
Solution Approach 1:
The division structure serves as an intermediary element that can be integrated into existing manufacturing workflows. The division liner pattern and connection metal pattern are formed using standard deposition and etching processes, acting as intermediate layers between existing structure elements. This approach reduces parasitic capacitance while adding minimal complexity to the manufacturing sequence.
Solution Approach 2:
The division structure is segmented into distinct functional components (division liner pattern for isolation and connection metal pattern for electrical connection) that can be formed in separate process steps. This segmentation allows each component to be optimized and controlled independently, reducing overall manufacturing complexity while achieving the reliability benefit of reduced parasitic capacitance.
Data Source
AI summary
A three-dimensional semiconductor device may include a first active region, which includes a first channel pattern and a first source/drain pattern connected to each other, on a substrate, a second active region, which includes a second channel pattern and a second source/drain pattern connected to each other, on the first active region, a gate electrode on the first and second channel patterns, a bottom active contact electrically connected to the first source/drain pattern and extended from the first source/drain pattern in a first direction, a lower metal layer provided below the bottom active contact, the lower metal layer including bottom via patterns and bottom interconnection lines electrically connected to the bottom active contact, and a division structure electrically connected to at least one of the bottom via patterns. The division structure may include a division liner pattern and a connection metal pattern penetrating the same.