3D Stacked Transistor Structure With Stepwise Insulation Isolation
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to operational property deterioration and challenges in achieving high-performance devices with increased integration density and improved electrical characteristics.
Innovation Solution
A three-dimensional semiconductor device design featuring vertically stacked transistors with a specific insulating structure and cutting pattern arrangement, including a first and second portion of the insulating structure with a stepwise surface, which enhances integration density and prevents short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS-FETs are scaled down to increase integration density, then the number of transistors per unit area increases, but operational properties deteriorate and electrical characteristics worsen
Solution Approach 1:
The patent transitions from two-dimensional planar transistor arrangement to three-dimensional vertically stacked transistor configuration. Multiple active regions (first, second, third, fourth active regions) are stacked vertically with corresponding gate electrodes, allowing integration density to increase by utilizing the vertical dimension while maintaining adequate transistor dimensions for reliable operation.
Solution Approach 2:
The transistor structure is segmented into multiple discrete active regions (first, second, third, fourth active regions) stacked vertically, each with its own gate electrode. This segmentation allows each transistor to maintain sufficient operational characteristics while achieving high integration density through vertical stacking.
2Quantity of substance
If vertically stacked transistors are implemented to increase integration density, then more transistors fit in the same area, but short circuit risks increase between adjacent structures
Solution Approach 1:
An insulating structure is introduced as an intermediary element disposed between adjacent vertically stacked transistor structures. This insulating structure includes first, second, third, and fourth portions that are positioned between corresponding active regions of adjacent transistors, providing electrical isolation and preventing short circuits while allowing the vertically stacked configuration to maintain high integration density.
3Reliability
If complex insulating structures with stepwise surfaces are added to prevent short circuits, then short circuit prevention is improved, but device complexity increases
Solution Approach 1:
The insulating structure exhibits local quality variations through its stepwise configuration, where different portions (first, second, third, fourth portions) are positioned at different vertical levels between adjacent active regions. This localized insulation approach provides effective short circuit prevention at each interface while maintaining overall structural organization and manageable complexity.
Data Source
AI summary
A three-dimensional semiconductor device may include a lower active region on a substrate, including a lower channel pattern and a lower source/drain pattern connected thereto, an upper active region on the lower active region, including an upper channel pattern and an upper source/drain pattern connected thereto, a gate electrode disposed on the lower and upper channel patterns and extended in a first direction, and an insulating structure disposed at a side of the lower and upper active regions and extended in a second direction, the first and second directions being parallel to a top surface of the substrate. The insulating structure may include a first portion, adjacent to the lower active region, and a second portion, provided on the first portion and adjacent to the upper active region. A side surface of the insulating structure may have a stepwise structure at a boundary between the first and second portions.