3D Stacked Semiconductor Transistors Using Ion-Cut Layer Transfer
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Solution Overview
Problem
Current 3D stacked integrated circuit technologies face challenges in constructing transistors above wiring layers at temperatures below 400°C, leading to misalignment issues and low connectivity between layers, which limits the density of connections and degrades transistor performance.
Innovation Solution
The use of ion-cut layer transfer techniques to construct single-crystal silicon transistors atop wiring layers at temperatures below 400°C, allowing for high-density connections and self-aligned transistor layers, and the implementation of junction-less transistors to reduce high-temperature source-drain junction processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are constructed above wiring layers at high temperatures (>700°C), then transistor performance is improved, but the bottom wiring layer gets damaged
Solution Approach 1:
The patent divides the 3D stacked chip into separate layers (bottom transistor layer, bottom wiring layer, top transistor layer, top wiring layer) that can be constructed independently at appropriate temperatures, then bonded together. This segmentation allows each layer to be processed at optimal temperatures without damaging other layers.
Solution Approach 2:
The bottom wiring layer is constructed at low temperature (<400°C) before the top transistor layer is formed. This preliminary construction of temperature-sensitive components protects them from subsequent high-temperature processing of the transistor layer.
2Device complexity
If wafer bonding is used to stack two wafers, then 3D integration is achieved, but alignment misalignment and large contact size are required
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertically-oriented transistors, enabling stacking of multiple transistor layers above wiring layers. This dimensional change allows for higher integration density while maintaining alignment precision through self-aligned fabrication processes.
Solution Approach 2:
The patent replaces mechanical alignment methods with self-aligned fabrication processes, where subsequent layers are automatically positioned relative to previous layers through the fabrication process itself, eliminating alignment errors from manual or mechanical positioning.
3Reliability
If Through-Silicon Via (TSV) contacts are used for inter-layer connections, then electrical connectivity is achieved, but contact density is limited due to etching difficulties
Solution Approach 1:
The patent replaces vertical TSV contacts with horizontally-oriented interconnect structures that extend laterally between stacked transistor layers. This dimensional change from vertical to horizontal connectivity allows for higher contact density as contacts can be formed along the edges of stacked structures rather than requiring deep vertical etching through the entire stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the construction of 3D stacked semiconductor chips with high-density connections between layers and improved transistor performance by aligning top-level transistors with bottom-level wiring and transistor layers, reducing thermal stress and enhancing connectivity.
Implementation Method 1
The use of ion-cut layer transfer techniques to construct single-crystal silicon transistors atop wiring layers at temperatures below 400°C
Data Source
AI summary
A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.