3D Stacking Semiconductor Device with Interlaced Photoresist Etching
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to increase circuit density within a fixed volume, which is essential for the development of lightweight, thin, and compact electronic products, while existing technologies struggle to efficiently stack semiconductor elements effectively.
Innovation Solution
A 3D stacking semiconductor device manufacturing method involving interlaced conductive and insulating layers, where photoresist layers are used to etch and trim the structures in specific directions, forming a matrix of contact points and conductive lines, allowing for compact stacking and efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D semiconductor layout is used, then manufacturing process is simple, but circuit density and device functionality are limited
Solution Approach 1:
The patent transitions from conventional 2D semiconductor layout to 3D stacking architecture, utilizing the vertical dimension to increase circuit density. Multiple semiconductor layers are stacked vertically with conductive layers connecting different levels, enabling higher device functionality within the same footprint area.
Solution Approach 2:
The semiconductor device is divided into multiple functional layers including active device layers, conductive layers, and insulating layers. Each layer is segmented into discrete units that can be independently formed and connected, allowing complex functionality to be built through systematic layering and stacking.
2Quantity of substance
If more semiconductor layers are stacked to increase density, then circuit density improves, but manufacturing precision requirements increase
Solution Approach 1:
Conductive layers are formed in advance within the stacking structure before final device assembly. These pre-formed conductive pathways serve as alignment references and connection templates, enabling precise positioning of subsequent layers and reducing the precision burden on final assembly operations.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between conductive layers and semiconductor active layers. These insulating layers provide mechanical spacing, electrical isolation, and alignment registration features that facilitate precise stacking while maintaining manufacturing feasibility.
3Reliability
If conductive lines are extended to connect multiple contact points, then electrical connectivity improves, but device area increases
Solution Approach 1:
Electrical connections transition from planar 2D routing to 3D vertical routing through conductive layers. Contact points on different semiconductor layers are connected via vertical conductive pathways, dramatically reducing the horizontal area required for interconnections compared to surface-mounted routing.
Solution Approach 2:
Conductive lines are nested within dedicated conductive layers that are embedded in the stacking structure. Multiple conductive pathways are nested at different vertical levels, allowing dense interconnection networks to be packed into a compact volume without planar routing conflicts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of densely packed 3D semiconductor devices with compactly stacked conductive layers and closely arranged conductive lines, enhancing circuit density and reducing device volume, thereby addressing the need for smaller and more efficient semiconductor elements.
Implementation Method 1
The first photoresist layer covers part of the surface of the stacking structures. The stacking structures are etched P-1 times by using the first photoresist layer as a mask.
Implementation Method 2
The stacking structures are etched P-1 times by using the first photoresist layer as a mask. In each step of etching the stacking structures, the stacking structures are etched for a thickness of one layer.
Data Source
AI summary
A 3D stacking semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. N layers of stacking structures are provided. Each stacking structure includes a conductive layer and an insulating layer. A first photoresist layer is provided. The stacking structures are etched P-1 times by using the first photoresist layer as a mask. A second photoresist layer is provided. The stacking structures are etched Q-1 times by using the second photoresist layer as a mask. The first photoresist layer is trimmed along a first direction. The second photoresist layer is trimmed along a second direction. The first direction is different from the second direction. A plurality of contact points are arranged along the first and the second directions in a matrix. The included angle between the first direction and the second direction is an acute angle.