3D Standard Cell Layout for Shorter Signal Paths and Lower Power
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Solution Overview
Problem
Existing semiconductor devices face challenges in improving performance and reducing power consumption due to the integration of combinational and sequential logic circuits, which are often connected through lengthy signal transmission paths and require complex wiring patterns.
Innovation Solution
The solution involves separating combinational logic circuits and sequential logic circuits into different layers, with combinational logic circuits in one layer and sequential logic circuits in another, connected by interlayer vias, and optimizing power supply paths to reduce complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If combinational logic circuits and sequential logic circuits are integrated in the same layer, then device area is reduced, but signal transmission path length increases and power consumption increases
Solution Approach 1:
The patent divides the semiconductor device into multiple layers, with combinational logic circuits placed in a first layer and sequential logic circuits placed in a second layer. This segmentation separates circuits that were previously mixed in the same layer, allowing signal transmission paths to be shortened within each layer while maintaining compact overall device area through vertical stacking.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional vertical stacking approach. By utilizing the vertical dimension to separate combinational and sequential logic circuits into different layers, the patent reduces in-plane signal transmission distances and enables more efficient wiring patterns while maintaining high device integration density.
2Length of moving object
If combinational logic circuits and sequential logic circuits are separated into different layers, then signal transmission path length is reduced, but device complexity increases
Solution Approach 1:
The patent segments the device into functionally distinct layers, with each layer dedicated to specific circuit types. This segmentation simplifies the wiring and signal routing within each layer, as circuits in the same layer can be interconnected more directly without needing to route signals through multiple layers, thereby reducing overall device complexity despite the multi-layer structure.
Solution Approach 2:
The patent applies local quality by optimizing the wiring and interconnection structures specific to each layer's circuit type. Combinational logic circuits in the first layer have wiring patterns optimized for combinational logic, while sequential logic circuits in the second layer have wiring patterns optimized for sequential logic, reducing the need for complex universal wiring patterns.
3Ease of manufacture
If circuits are densely integrated in a single layer, then manufacturing process is simplified, but signal transmission efficiency decreases
Solution Approach 1:
The patent uses vertical stacking to create multiple layers, each optimized for specific circuit functions. This three-dimensional arrangement maintains manufacturing simplicity by using standard multi-layer semiconductor fabrication processes while dramatically improving signal transmission efficiency by reducing the physical distance signals must travel between circuits.
Solution Approach 2:
The patent segments circuits into functionally specialized layers, allowing each layer to be optimized for its specific circuit type. This segmentation enables more efficient signal transmission within each layer while the overall manufacturing process remains relatively simple, leveraging established multi-layer semiconductor manufacturing techniques.
Data Source
AI summary
A semiconductor device includes: a first layer including a first semiconductor substrate, a plurality of first standard cell regions defined in the first semiconductor substrate, and a plurality of first standard cells disposed in the plurality of first standard cell regions; and a second layer including a second semiconductor substrate, a plurality of second standard cell regions defined in the second semiconductor substrate, and a plurality of second standard cells disposed in the plurality of second standard cell regions, the second layer being stacked with the first layer in a vertical direction perpendicular to an upper surface of the first semiconductor substrate, wherein the plurality of first standard cells provide combinational logic circuits, and the plurality of second standard cells provide at least some of sequential logic circuits, a clock gate circuit, a power circuit, and a level shifter circuit.