3D Static RAM Core Cell Vertical Stacking Integration
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Solution Overview
Problem
Current technologies face challenges in integrating a high number of semiconductor elements per unit area due to the complexity of patterning different types of organic transistors, which limits the degree of integration and area efficiency in memory elements.
Innovation Solution
A 3D static RAM core cell with a vertically stacked structure, where six thin-film transistors are arranged in three layers, with electrical connections between layers, allowing for the same type of organic transistors to be stacked and reducing the need for complex patterning of different types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If organic transistors of different types are formed on a single surface to create memory elements, then the memory element can function properly, but the patterning process becomes complicated and the area occupied increases
Solution Approach 1:
The patent transitions from planar arrangement to vertical stacking by forming transistor layers at different heights (first transistor layer, second transistor layer, third transistor layer). This dimensional change allows transistors to be stacked vertically rather than arranged horizontally, simplifying the patterning process while maintaining memory functionality through electrical connections between layers.
Solution Approach 2:
The memory element is segmented into multiple transistor layers (first, second, and third transistor layers) stacked vertically. Each layer contains specific transistors (switching transistors and data storage transistors) that are electrically connected through conductive vias, dividing the complex patterning into simpler, sequential layer formation processes.
2Productivity
If more semiconductor elements are integrated per unit area to increase degree of integration, then memory capacity improves, but the area occupied by each element increases due to complex patterning
Solution Approach 1:
By stacking transistor layers vertically (first transistor layer at lower level, second and third transistor layers at higher levels), the patent achieves higher degree of integration within a smaller footprint area. The vertical arrangement allows more elements to be packed into the same planar space, increasing productivity without proportionally increasing the occupied area.
Solution Approach 2:
The patent implements a nested structure where transistor layers are stacked one above another, with each layer containing transistors that are electrically connected to layers above or below. This nesting approach maximizes the use of vertical space, allowing multiple functional elements to be integrated within a compact three-dimensional structure.
Data Source
AI summary
Disclosed is a 3D static RAM core cell having a vertically stacked structure, including six thin-film transistors each having a gate electrode, a source electrode and a drain electrode, the static RAM core cell including two switching thin-film transistors, each connected to a bit line and a word line to select recording and reading of data, and four data-storage thin-film transistors connected to a power supply voltage (Vdd) or a ground voltage (Vss) to record and read data, the static RAM core cell including a first transistor layer including two thin-film transistors selected from among the six thin-film transistors, a second transistor layer disposed on the first transistor layer and including two thin-film transistors selected from among the remaining four thin-film transistors, and a third transistor layer disposed on the second transistor layer and including the remaining two thin-film transistors, at least one electrode of the first transistor layer and at least one electrode of the second transistor layer being electrically connected to each other, and at least one electrode of the second transistor layer and at least one electrode of the third transistor layer being electrically connected to each other. Thereby, the static RAM core cell is configured such that organic transistors of the same type are arranged in the same plane and are vertically stacked, thus omitting a complicated patterning process for forming organic transistors of different types upon fabrication of a memory element, and also reducing the area occupied by the memory element to thereby increase the degree of integration of semiconductor circuits.