3D Storage Cell Array Scalable Word Line Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The density of memory chips is limited by the inability of word line wiring to scale down as rapidly as storage cell size, leading to increased lateral expansion of word lines beyond the array structure dimensions, hindering the achievement of disk drive-like storage densities in semiconductor memory devices.
Innovation Solution
A three-dimensional storage cell array with a highly dense and scalable word line design, where word lines are distributed outward along the X-axis instead of laterally, utilizing a staircase structure with alternating conductive and dielectric layers and additional space for vias and transistors, allowing for increased density and scalability by forming neighboring steps in the staircase structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If word line wiring is designed to connect to storage cells in traditional lateral configuration, then connectivity is achieved, but lateral expansion increases and storage density decreases
Solution Approach 1:
The patent transitions word line wiring from a traditional lateral (2D) configuration to a vertical (3D) configuration by forming word lines that extend in the vertical direction through alternating conductive and dielectric layers. This dimensional change allows word lines to connect to storage cells without requiring lateral expansion, thereby increasing storage density while maintaining connectivity.
Solution Approach 2:
The patent implements a nested structure where word line wiring is embedded within alternating conductive and dielectric layers, forming a staircase-like configuration. The word lines are nested within the vertical stack, allowing multiple word lines to be integrated in the vertical dimension without increasing lateral footprint, thus resolving the contradiction between connectivity and storage density.
2Quantity of substance
If storage cell size is reduced to increase density, then storage capacity increases, but word line wiring cannot scale down proportionally
Solution Approach 1:
The patent addresses the scaling limitation by moving word line wiring into the vertical dimension through alternating conductive and dielectric layers. This allows storage cell size to be reduced in the lateral direction while word line wiring maintains its dimensions by extending vertically, effectively decoupling the scaling of storage cells from the scaling constraints of word line wiring.
Solution Approach 2:
The patent segments the word line wiring into multiple discrete layers separated by dielectric layers, forming a staircase structure. This segmentation allows each word line layer to be independently formed and scaled, enabling better control over wiring dimensions and facilitating continued scaling of storage cells without proportionally reducing word line dimensions.
3Quantity of substance
If traditional word line configuration is used, then manufacturing is straightforward, but storage density is limited
Solution Approach 1:
The patent increases storage density by reconfiguring word lines into the vertical dimension with alternating conductive and dielectric layers. While this increases structural complexity compared to traditional lateral wiring, the vertical configuration enables higher density by utilizing the third dimension, accepting the trade-off of increased manufacturing complexity for significant density improvement.
Solution Approach 2:
The patent merges multiple word line layers into a unified staircase structure formed through alternating deposition of conductive and dielectric materials. This merging approach, while structurally more complex than single-layer wiring, enables compact integration of multiple word lines in a systematic manner that achieves high storage density.
Data Source
AI summary
An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.