3D Submount With Embedded Cooling Channels For VCSEL Arrays
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Solution Overview
Problem
Current semiconductor laser technologies face challenges in achieving high power output while maintaining tight-pitch packing and resolving thermal crosstalk issues, which are essential for applications like high-resolution printing and lidar systems.
Innovation Solution
The development of a 3D packaging system for semiconductor lasers that includes a 3D submount with embedded cooling channels, integrated slots for driver chips and optics, and a multi-row interposer design, along with a Selfoc lens array for efficient thermal management and high-resolution imaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If VCSEL aperture size is increased to produce high power output, then light output power is improved, but device size increases making tight-pitch packing difficult
Solution Approach 1:
The patent transitions from planar 2D VCSEL arrays to three-dimensional stacked architectures, enabling multiple VCSEL layers to be vertically integrated. This dimensional change allows high power output through stacked emitters while maintaining small footprint for tight-pitch packing, as the vertical stacking consolidates multiple light sources into a compact volume.
Solution Approach 2:
The patent implements nested integration where multiple VCSEL layers are stacked within a single device footprint, with each layer containing multiple VCSELs. This nesting approach allows high power output from multiple stacked layers while maintaining compact device dimensions suitable for tight-pitch arrays.
2Manufacturing precision
If VCSELs are packed into tight-pitch arrays to achieve high resolution, then spatial resolution is improved, but thermal crosstalk increases affecting performance
Solution Approach 1:
The patent employs vertical stacking of VCSEL layers separated by spacing layers, creating vertical separation between heat-generating elements. This three-dimensional arrangement with spaced-apart layers reduces thermal crosstalk while maintaining tight horizontal pitch for high spatial resolution, as heat can dissipate vertically through the spaced structure.
Solution Approach 2:
The patent introduces intermediate spacing layers between stacked VCSEL layers, which act as thermal isolation barriers. These intermediary layers reduce thermal crosstalk between adjacent VCSELs while allowing optical functionality to be maintained, enabling tight-pitch high-resolution arrays without performance degradation from heat interference.
3Quantity of substance
If multiple high power lasers operate in a small region to achieve tight-pitch packing, then array density is improved, but thermal load density increases requiring enhanced cooling
Solution Approach 1:
The patent implements vertical stacking of multiple VCSEL layers with spacing between them, distributing thermal load across three-dimensional space rather than concentrating it in a single plane. This vertical distribution of heat-generating elements across multiple spaced layers reduces thermal load density while maintaining high array density through multi-layer integration.
Solution Approach 2:
The patent segments the VCSEL array into multiple discrete stacked layers with spacing between them, allowing thermal management for each layer independently. This segmentation distributes the aggregate thermal load across multiple separated thermal zones, reducing peak thermal density while maintaining high overall array density through vertical integration.
4Length of moving object
If VCSEL aperture is reduced to enable tight-pitch packing, then packing density is improved, but light output power decreases
Solution Approach 1:
The patent nests multiple VCSEL layers within a compact vertical stack, where each layer contains multiple small-aperture VCSELs configured for tight-pitch packing. The nested multi-layer structure compensates for reduced individual aperture size by aggregating light output from numerous stacked VCSELs, achieving high total power while maintaining small device footprint.
Solution Approach 2:
The patent transitions to three-dimensional vertical stacking of multiple VCSEL layers, enabling compensation for reduced aperture size through vertical integration. By stacking multiple layers of small-aperture VCSELs, the system achieves high total light output power while maintaining small horizontal footprint for tight-pitch packing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-power, independently-addressable VCSEL arrays to achieve resolutions greater than 300 dpi, effectively managing thermal loads and maintaining high light output, thus addressing the limitations of existing technologies in tight-pitch packing and thermal management.
Implementation Method 1
a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept cooling liquid therethrough
Implementation Method 2
the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel
Data Source
AI summary
A 3D package for semiconductor thermal management can include a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept cooling liquid therethrough, a first tubular connection for providing cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel. Integrated slots can be provided for accepting and mounting semiconductor components. Mounting holes can be formed in the mechanical block for securing optical elements. At least one semiconductor laser array die can be secured to the mechanical block at the integrated slots, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel.