3D Packaging Substrate With Sidewall Pads for Compact Thermal Layout
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Solution Overview
Problem
Current circuit board packaging technologies, both horizontal and vertical, face limitations in design freedom, occupy large space, and hinder heat dissipation due to densely arranged components, restricting miniaturization and high integration.
Innovation Solution
A substrate manufacturing method for three-dimensional packaging involves a base plate with dielectric material, sidewall pads, and through-hole pillars, allowing for the creation of cavities and multiple circuit layers, enabling the placement of active and passive devices in a cavity with increased design freedom and reduced space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If pads are confined to the same circuit layer, then circuit design is simplified, but design freedom is limited
Solution Approach 1:
The patent introduces side wall pads that extend vertically from the circuit board substrate, transitioning the pad structure from a two-dimensional planar configuration to a three-dimensional structure. This dimensional change allows pads to be positioned on the side walls of cavities rather than being confined to circuit layers, providing additional spatial freedom for circuit design while maintaining manageable complexity through structured implementation
2Volume of stationary object
If components are densely arranged or stacked, then space utilization improves, but heat dissipation effect deteriorates
Solution Approach 1:
The patent segments the package structure by creating separate cavities within the circuit board substrate, each capable of housing individual components. This segmentation allows for optimized component placement and spacing within each cavity, preventing excessive density while improving overall space utilization. The side wall pads provide dedicated connection points that facilitate this segmented arrangement
3Adaptability or versatility
If multiple chips are packaged horizontally or vertically, then multifunction is achieved, but occupation area increases
Solution Approach 1:
The patent utilizes the vertical dimension by extending pads along the side walls of cavities and positioning components within three-dimensional cavity spaces. This approach allows multiple chips and components to be packaged in a compact volume by exploiting the Z-axis space, thereby achieving multifunctional capabilities without proportionally increasing the planar occupation area of the circuit board
Data Source
AI summary
Disclosed is a substrate manufacturing method for realizing three-dimensional packaging, which includes: preparing a base plate, the base plate including a dielectric material layer, a first sidewall pad, a first through-hole pillar and a cavity, the cavity being filled with a first metal block; processing a first circuit layer and a second circuit layer, the first circuit layer including a first padding plate and a second metal block, and the second circuit layer including a second padding plate and a plurality of pin pads; processing and laminating interlayer through-hole pillars; processing a third circuit layer and a fourth circuit layer, the third circuit layer including a second sidewall pad and the fourth circuit layer including a routing circuit; and etching to expose the first sidewall pad, the second sidewall pad and the pin pads.