3D Synapse Stack Architecture for Dense and Reliable Neural Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing neural network implementations using RRAM and SRAM devices face issues with reliability and integration, leading to high power consumption and limited integration capabilities.
Innovation Solution
A three-dimensional synapse device stack comprising a substrate, body electrode, semiconductor bodies, insulating layers, sources, drains, and word lines, configured in a stackable form to create AND-type or NOR-type synapse arrays, with insulator stacks for improved integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If Memristor-based synapses are used to implement neural networks, then power consumption is reduced, but device reliability is poor and dispersion between devices is large
Solution Approach 1:
The patent transitions from planar 2D device layout to vertical 3D stacked architecture. Multiple synapse devices are stacked vertically along the Z-axis, with body electrodes forming columns and word lines intersecting at different heights. This three-dimensional arrangement increases integration density while maintaining device performance and reliability characteristics.
Solution Approach 2:
The synapse array is segmented into multiple independently controllable devices within the stacked structure. Each synapse device consists of distinct body electrode segments, semiconductor bodies, and insulating layers that can be selectively programmed and erased through word line control, enabling reliable individual device operation within the integrated stack.
2Reliability
If SRAM devices are used to implement neural networks, then reliability is good, but integration density is low due to multiple devices required
Solution Approach 1:
Multiple synapse devices are merged into a single integrated stacked structure sharing common source and drain line electrodes. The body electrodes of multiple devices are combined to form shared column structures, while semiconductor bodies and insulating layers are stacked vertically. This merging achieves high integration density while maintaining the reliability characteristics of individually controllable devices through word line selection.
3Device complexity
If traditional planar synapse arrays are used, then device structure is simple, but degree of integration is limited
Solution Approach 1:
The patent extends the device architecture from planar 2D to vertical 3D configuration. Synapse devices are stacked along the vertical Z-axis with body electrodes forming columns, semiconductor bodies alternating with insulating layers, and word lines intersecting at different heights. This dimensional transition achieves high integration density while building upon relatively simple planar fabrication processes.
Solution Approach 2:
The stacked structure employs a nested arrangement where semiconductor bodies, insulating layers, and electrode structures are nested vertically within each other. Multiple synapse devices are nested along the Z-axis, with each device's components contained within the vertical space defined by the stacked architecture, maximizing space utilization and integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D synapse device stack enhances integration and operational reliability, allowing selective programming and erasing operations, and facilitates integration with CMOS circuits.
Implementation Method 1
a plurality of insulator stacks positioned between the word lines and the semiconductor bodies
Implementation Method 2
a body electrode having a pillar shape, made of an electrically conductive material and disposed on the substrate; a plurality of semiconductor bodies made of a semiconductor material, disposed on the outer circumferential surface and the surface of the third oxide layers, electrically connected to the body electrode
Data Source
AI summary
Provided is a 3D synapse device stack, a 3D stackable synapse array using the same, and a method for manufacturing the 3D synapse device stack. The 3D synapse device stack comprises: a body electrode disposed on a substrate in a vertical direction; a plurality of first insulating layers and third oxide layers alternately stacked on the outer circumferential surface of the body electrode; a plurality of semiconductor bodies disposed on an outer circumferential surface of the third oxide layer; a plurality of sources alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a first side surface of the body electrode; a plurality of drains alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a second side surface of the body electrode; a plurality of word lines alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a third side surface of the body electrode; and an insulator stack positioned between the word line and the semiconductor body. The semiconductor body, the source, the drain, the insulator stack and the word line located on the same layer on the outer peripheral surface of the body electrode constitute a synapse device, or a part thereof. The synapse device stack may implement an AND-type or NOR-type synapse array.