3D System-Level Packaging Multi-Layer Integration
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Solution Overview
Problem
Current wafer-level packaging technologies, such as fan-out wafer level packaging, are limited in supporting multi-layer structures with complex connections and system-level integration, primarily enabling single chip functions with the need for external addition of peripheral circuits like capacitors, inductors, or resistors, and fail to achieve desired system-level packaging integration.
Innovation Solution
A 3D system-level packaging method involving a packaging substrate with a glue layer, multiple chip layers, sealant layers, and interconnecting vertical and horizontal metal wiring layers, allowing for the formation of multi-layer structures with increased integration by stacking and connecting chip and passive device layers through vias and wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If fan-out wafer level packaging method is used, then chip size miniaturization and cost reduction are achieved, but system-level integration capability deteriorates
Solution Approach 1:
The patent transitions from traditional planar (2D) packaging to three-dimensional (3D) stacked packaging. Multiple chip layers are vertically stacked and interconnected through through-silicon vias (TSVs) and redistribution layers, enabling system-level integration while maintaining miniaturization benefits. This dimensional change allows complex interconnections and peripheral circuits to be integrated within the package volume rather than requiring external components.
2Ease of manufacture
If single-layer packaging structure is used, then manufacturing process is simple, but connection complexity for multi-layer structures deteriorates
Solution Approach 1:
The packaging structure is segmented into multiple functional layers including chip layers, sealant layers, redistribution layers, and interconnection layers. Each layer has a specific function and can be processed independently to some extent. The segmentation allows complex multi-layer connections to be built up systematically through repeated patterning and stacking operations, making the manufacturing process manageable despite the increased device complexity.
Solution Approach 2:
Through-silicon vias (TSVs) are formed and filled with conductive material before the final chip stacking operation. Redistribution layers are pre-patterned on the substrate before chips are attached. These preliminary actions prepare the interconnection infrastructure in advance, enabling subsequent chip layers to be connected systematically without requiring complex post-assembly routing operations.
3Adaptability or versatility
If peripheral circuits are added externally, then single chip function is maintained, but packaging integration degree deteriorates
Solution Approach 1:
Active chips containing logic circuits and passive components containing peripheral circuits (capacitors, inductors, resistors) are merged into a single integrated package structure. The passive components are formed as separate layers or regions within the package, and interconnections between active and passive components are established through the same redistribution layer and via infrastructure. This merging achieves system-level integration where peripheral circuits are no longer external additions but integrated parts of the packaging structure.
Data Source
AI summary
A 3D system-level packaging method includes providing a packaging substrate, forming a glue layer on the substrate, and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer. The method also includes forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, and each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers.