3D Semiconductor Test Circuit Soft Error Detection
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Solution Overview
Problem
Current test circuits for detecting soft errors in 3D semiconductor devices require multiple Multiple Input Signature Registers (MISRs) for each chip, leading to increased hardware overhead and test time, which is inefficient and costly, especially as the number of chips increases.
Innovation Solution
A test circuit configuration for 3D semiconductor devices that uses one MISR per chip, with error detection via a comparator and SER counter, utilizing Through Silicon Vias (TSVs) for inter-chip signal comparison, allowing simultaneous testing and reducing hardware overhead and test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two MISRs are provided for every chip in a 3D semiconductor device, then soft errors can be detected through twin tests, but hardware overhead increases and test time increases
Solution Approach 1:
The patent divides the 3D semiconductor device into multiple chips (first chip and second chip), with each chip containing its own MISR. This segmentation allows each MISR to independently compress test results from its respective chip, eliminating the need for duplicate MISRs on each chip while maintaining soft error detection capability through inter-chip comparison.
Solution Approach 2:
The patent merges the test result compression function across multiple chips by having each chip's MISR compress its local test results and then comparing the compressed results through TSVs. This merging approach consolidates the error detection function at the chip level rather than requiring redundant MISRs on every chip, reducing overall hardware overhead.
2Reliability
If two MISRs are provided for every chip in a 3D semiconductor device, then soft errors can be detected through twin tests, but test time increases
Solution Approach 1:
By segmenting the test function across multiple chips with each chip having its own MISR, the patent enables parallel test execution. Each MISR independently compresses test results from its chip simultaneously, and the inter-chip comparison through TSVs occurs in parallel, significantly reducing total test time compared to sequential twin tests on single-chip configurations.
Solution Approach 2:
The patent maintains continuous useful action by enabling simultaneous test result compression in multiple MISRs across different chips. The inter-chip comparison through TSVs allows continuous error detection without interrupting the test flow, maximizing test efficiency and minimizing total test time.
3Reliability
If multiple MISRs are provided in each chip, then soft error detection is possible, but the configuration becomes inefficient and costly as the number of chips increases
Solution Approach 1:
The patent segments the error detection function by placing one MISR per chip rather than multiple MISRs per chip. This segmentation scales efficiently with the number of chips, as each MISR handles only its local chip's test results. The inter-chip comparison through TSVs provides a scalable architecture that maintains testing efficiency even as the device grows to include more chips.
Solution Approach 2:
Each MISR in the patent serves multiple functions: it compresses test results from its local chip, transmits the compressed result through TSVs to other chips, and participates in inter-chip error detection. This multi-functionality eliminates the need for dedicated comparison hardware on each chip, improving productivity and reducing cost as the device scales.
Data Source
AI summary
Disclosed herein is a test circuit for a 3D semiconductor device for detecting soft errors and a method for testing thereof. The test circuit includes a first Multiple Input Signature Register (MISR) disposed in a first semiconductor chip, the first MISR compressing a first test result signal corresponding to a test pattern, a second MISR disposed in a second semiconductor chip stacked on or under the first semiconductor chip, the second MISR compressing a second test result signal corresponding to the test pattern, and a first error detector to detect a soft error by comparing a first output signal output from the first MISR with a second output signal output from the second MISR.