3D Thin-Film Transistor Channel Formation Without Sidewall Stringers

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Solution Overview

Problem

In the manufacturing of 3-dimensional arrays of thin-film transistors, existing processes face challenges with excessive thinning of channel semiconductor material adjacent the body oxide layer and the formation of undesirable stringers on the sidewalls of trenches during the separation etch, which can lead to contamination and reduced performance.

Innovation Solution

A process involving the use of isolation layers with varying dopant concentrations, followed by annealing and selective etching, to chemically convert and selectively remove the channel semiconductor material from the sidewalls of trenches, ensuring even dopant distribution and preventing excessive thinning and stringer formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a separation etch is performed to remove channel semiconductor material from trench sidewalls, then isolation between adjacent active strips is improved, but excessive thinning of channel material and stringer formation occur

Engineering Contradiction:

Improveisolation between active stripsVSAvoidintegrity of channel semiconductor material

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

A dopant layer is deposited on the trench sidewalls before the separation etch process. This preliminary doping action modifies the chemical properties of the channel material adjacent to the sidewalls, making it more resistant to etching. When the separation etch is subsequently performed, the doped region protects the channel material from excessive removal, preventing both thinning and stringer formation while still achieving adequate isolation between active strips.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If the separation etch is made more aggressive to improve isolation, then trench sidewall cleaning is improved, but contamination and stringer formation increase

Engineering Contradiction:

Improvetrench sidewall cleaningVSAvoidcontamination and stringer formation

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The dopant layer, which could be considered an additional processing step, actually converts the potential harm of aggressive etching into a benefit. By introducing the dopant layer, the etch process can be made more aggressive to achieve better sidewall cleaning, while the doped region simultaneously protects against the harmful effects of excessive material removal and stringer formation. The harmful aggressive etching is thus transformed into a beneficial process that achieves both cleaning and protection.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If dopant concentration is increased to prevent material removal, then channel material protection is improved, but threshold voltage control precision may be affected

Engineering Contradiction:

Improvechannel material protectionVSAvoidthreshold voltage control

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The dopant layer provides localized doping only in the regions adjacent to the trench sidewalls, rather than uniformly doping the entire channel. This local quality approach allows the channel material to be protected from etching at critical locations while maintaining precise threshold voltage control in the active channel regions. The spatially selective doping ensures that protection is provided exactly where needed without compromising overall device performance.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents excessive thinning and stringer formation, maintaining the integrity of the channel semiconductor material and allowing for precise control of dopant concentration to optimize the threshold voltage of thin-film transistors, enhancing their performance and reliability.

Implementation Method 1

annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer

Methodology Applied

Scientific EffectDiffusion: Diffusion

Data Source

PatentUS11844204B2Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array

Publication Date: 2023.12.12 SUNRISE MEMORY CORP

AI summary

A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.