3D Thin-Film Transistor Layout for Smaller Display Footprints
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Solution Overview
Problem
Conventional thin-film transistor (TFT) structures occupy large areas, hindering integrated design and efficient use of space in display products.
Innovation Solution
A thin-film transistor with a three-dimensional structure, where the gate, gate insulating layer, and semiconductor layer are sequentially disposed radially, and the source and drain are arranged at intervals along the axial or circumferential direction, reducing the occupied area and facilitating integrated design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar TFT structure is used, then the TFT can be easily manufactured with conventional processes, but the occupied area is large which hinders integrated design
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional structure where the gate electrode extends underneath the source and drain electrodes. This dimensional change allows the channel to be formed in the vertical direction beneath the source-drain region, effectively reducing the horizontal occupied area while maintaining the same channel length and transistor performance.
Solution Approach 2:
The gate electrode is positioned to extend underneath the source and drain electrodes, creating a nested configuration where the channel region is effectively nested within the projection area of the source and drain. This nesting arrangement allows the channel to utilize the vertical space beneath the source-drain structure, reducing the overall footprint of the transistor.
2Power
If the channel width is increased to enhance driving ability, then the output current increases, but the occupied area increases
Solution Approach 1:
By extending the gate electrode underneath the source and drain, the channel width can be increased in the vertical direction without increasing the horizontal footprint. The channel is formed in the region where the gate extends beneath the source-drain, allowing greater channel width while maintaining the same occupied area projection.
Solution Approach 2:
The gate electrode has different spatial extensions in different regions: it extends underneath the source and drain in the channel formation region, while maintaining appropriate spacing in other regions. This localized variation in gate extension allows optimization of channel width specifically where needed for current drive, without unnecessarily increasing the overall device area.
Data Source
AI summary
The present application discloses a thin-film transistor, a display panel, and an electronic device. The thin-film transistor includes a gate, a gate insulating layer, and a semiconductor layer sequentially disposed from an inside to an outside along a radial direction. The thin-film transistor further includes a source and a drain disposed on a side of the semiconductor layer and arranged at intervals, and the source and the drain are connected to the semiconductor layer.