3D TFT Ferroelectric Memory Array for Density and Retention
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in achieving high density and efficient data storage while maintaining fast write/read speeds and small form factors.
Innovation Solution
A 3D memory array is developed with vertically stacked memory cells, each comprising a thin film transistor (TFT) with a word line region as a gate electrode, bit line and source line regions as source/drain electrodes, and a memory film with an oxide semiconductor channel region and conductive features between the memory film and the oxide semiconductor channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D memory structures are used, then manufacturing is simpler, but device density is limited
Solution Approach 1:
The patent transitions from conventional 2D planar memory structures to a 3D vertically stacked architecture. Multiple memory cells are stacked along the vertical direction, with each cell containing a ferroelectric capacitor and transistor. This dimensional change enables significantly higher device density by utilizing the third dimension (vertical stacking) rather than only expanding in the planar direction.
2Quantity of substance
If memory cell size is reduced for high density, then storage capacity increases, but write/read speed may deteriorate
Solution Approach 1:
The patent employs ferroelectric materials with specific phase structures (orthorhombic, tetragonal, or rhombohedral phases) that exhibit fast polarization switching characteristics. By controlling the crystal phase and composition parameters of the ferroelectric material, the memory cell achieves both small size for high density and fast switching speeds for rapid write/read operations. The ferroelectric effect enables non-volatile storage with speeds comparable to volatile memory.
3Speed
If ferroelectric material is used for fast write/read, then speed is improved, but retention time may be insufficient compared to other non-volatile memories
Solution Approach 1:
The patent uses composite ferroelectric material systems, specifically hafnium-based ferroelectric materials (such as HfO2, HfZrO3, or Hf1-xZrxO2-y) that combine the fast switching properties of ferroelectrics with enhanced retention characteristics. The composite structure and specific composition ratios enable the material to maintain stable polarization states for extended periods, achieving retention times suitable for non-volatile memory applications while preserving fast write/read speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D memory array enhances device density, improves endurance of TFTs by reducing defects in the memory film-conductive feature interface, and increases retention time by providing better charge screening, thus addressing the limitations of existing memory technologies.
Implementation Method 1
Each memory cell includes a ferroelectric material and a channel region. The patent describes forming a memory device with ferroelectric random access memory (FeRAM) characteristics, utilizing the ferroelectric effect for data storage.
Implementation Method 2
Each memory cell includes a thin film transistor (TFT) with bit line and source line regions as source/drain electrodes, and an oxide semiconductor channel region.
Data Source
AI summary
A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line, an oxide semiconductor (OS) layer contacting a source line and a bit line, and a conductive feature interposed between the memory film and the OS layer. The memory film is disposed between the OS layer and the word line. A dielectric material covers sidewalls of the source line, the memory film, and the OS layer.