3D Through-Glass-Via Inductors for High Density Integration
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Solution Overview
Problem
As integrated circuits (ICs) become more complex and smaller, traditional inductor designs face challenges in increasing the number of inductors without proportionally increasing chip size, due to physical constraints and interference issues.
Innovation Solution
The development of three-dimensional through-glass-via (3D TGV) inductors, which utilize both the top and bottom wafers to form inductors with increased cross-sectional area, allowing for higher inductance density without expanding the chip footprint, by using conductive vias and traces to maximize inductance value and minimize space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional planar inductor designs are used, then the inductor structure is simple to manufacture, but the chip real estate required increases proportionally with the number of inductors
Solution Approach 1:
The patent transitions from traditional planar (2D) inductor designs to three-dimensional (3D) inductor structures using through-glass vias. The inductors are formed with conductive paths that extend vertically through the substrate, utilizing the third dimension (depth) to increase inductance density without proportionally increasing the chip footprint. This dimensional transformation allows multiple inductors to be stacked or arranged in vertical configurations, significantly reducing the area required per inductor while maintaining manufacturability through established via and trace fabrication processes.
2Area of stationary object
If inductors are packed closely together to reduce chip size, then the chip footprint decreases, but coupling and interference between inductors increases
Solution Approach 1:
By forming inductors with vertical conductive paths through the substrate using through-glass vias, the patent creates three-dimensional inductor structures that can be closely packed in the horizontal plane while maintaining electrical isolation. The vertical orientation and substrate separation allow inductors to be positioned closer together without experiencing the same degree of mutual coupling and interference as planar inductors, thus reducing harmful electromagnetic interactions while minimizing chip footprint.
3Quantity of substance
If the size of individual inductors is reduced to fit more on a chip, then more inductors can be integrated, but the inductance value and performance deteriorate
Solution Approach 1:
The patent forms inductors with vertical conductive paths extending through the substrate using through-glass vias, creating three-dimensional inductor structures. This vertical configuration increases the effective length and cross-sectional area of the inductor windings without increasing the horizontal footprint, thereby maintaining or even improving inductance values and quality factors while enabling higher integration density. The 3D structure allows more turns or longer conductor paths to be packed into a smaller planar area, preserving performance while increasing quantity.
Solution Approach 2:
The patent utilizes composite structures combining conductive materials (such as copper or aluminum) with the glass substrate and dielectric materials to form the inductor. The through-glass vias provide conductive pathways that integrate the metal traces with the substrate, creating a composite structure that optimizes both electrical performance and spatial efficiency. This composite approach allows for controlled impedance and optimized inductance values within the constrained 3D space.
Data Source
AI summary
Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.