3D Thyristor Memory Cell Structure for Density and Thermal Stability
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Solution Overview
Problem
Thyristor memory devices face challenges in achieving high memory density, thermal resistance, and cost-effectiveness due to limitations in material selection and manufacturing complexity, particularly in two-dimensional structures.
Innovation Solution
The development of a three-dimensional thyristor memory cell structure using un-doped semiconductor features made of different materials, such as SiGe and InAs, stacked vertically to minimize material usage and reduce thermal fluctuations, with a gate feature surrounding the semiconductor anode, allowing for improved thermal resistance and higher memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-dimensional thyristor memory structure is used, then the manufacturing process is simpler, but the memory density is lower
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by stacking semiconductor layers (N-doped, P-doped, N-doped) vertically to form a thyristor memory cell. This vertical stacking enables higher memory density by utilizing the third dimension (height) rather than only expanding in the planar direction, while maintaining compatibility with standard semiconductor manufacturing processes through sequential layer deposition and doping.
2Reliability
If more materials are used in the thyristor memory cell, then the performance is improved, but the material cost increases
Solution Approach 1:
The patent employs different semiconductor materials with specific properties in different regions of the thyristor memory cell. For example, SiGe may be used in certain layers to enhance carrier mobility while silicon is used in other layers for cost-effectiveness and process compatibility. This localized material selection optimizes device performance in critical regions while controlling overall material costs by not using expensive materials throughout the entire structure.
Solution Approach 2:
The thyristor memory cell utilizes composite semiconductor structures combining multiple materials such as silicon and SiGe in alternating doped layers. These composite material structures leverage the advantageous properties of each material (e.g., SiGe's high mobility in channel regions, silicon's maturity and low cost in substrate and isolation regions) to achieve superior overall device performance while managing material expenses through strategic material placement.
3Reliability
If the thyristor memory cell uses doped semiconductor features, then the electrical conductivity is improved, but the thermal resistance increases
Solution Approach 1:
The patent applies doping selectively in specific regions and layers of the thyristor memory cell rather than uniformly throughout. For instance, heavy doping is concentrated in contact regions and selectively in active channel regions to ensure low electrical resistance where needed, while lightly doped or undoped regions are maintained in areas where thermal conduction is critical, thereby balancing electrical conductivity requirements with thermal management needs.
Data Source
AI summary
A thyristor memory cell includes a semiconductor cathode, a first un-doped semiconductor feature connected to the semiconductor cathode, a second un-doped semiconductor feature connected to the first un-doped semiconductor feature, a semiconductor anode connected to the second un-doped semiconductor feature, and a gate feature disposed on the first un-doped semiconductor feature or the second un-doped semiconductor feature. Among the semiconductor cathode, the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor anode, the semiconductor anode has the highest bottom edge of conduction band, followed by the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor cathode in the given order; and the semiconductor anode has the highest top edge of the valence band, followed by the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor cathode in the given order.