3D Thyristor Memory Stack for High-Density Read Write Isolation
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Solution Overview
Problem
Traditional planar memory devices face limitations in size reduction due to process constraints, necessitating the development of three-dimensional (3D) memory devices to achieve higher integration.
Innovation Solution
A 3D memory with a thyristor configuration featuring a stacked structure, annular channel layers, p-type and n-type doped regions, source and bit line pillars, and gate insulating layers, utilizing metal gates and polysilicon or metal pillars, with a slit to separate gates and insulating layers, and specific voltage applications for programming, erasing, and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional planar memory device structure is used, then manufacturing process is simple, but size reduction is limited due to process constraints
Solution Approach 1:
The patent transitions from traditional planar (2D) memory structure to a three-dimensional stacked structure with multiple levels. The memory device comprises multiple bit line pillars, source line pillars, and channel layers stacked vertically, enabling higher integration density by utilizing the third dimension (vertical stacking) to overcome the size reduction limitations of planar devices.
Solution Approach 2:
The patent implements a nested structure where bit line pillars and source line pillars are vertically stacked with channel layers in between. Each level consists of bit line pillar-channel layer-source line pillar units stacked alternately, creating a compact nested arrangement that maximizes storage density within a small footprint area.
2Productivity
If 3D stacked structure with thyristor configuration is implemented, then integration capability is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory device into multiple discrete levels, each comprising bit line pillars, source line pillars, and channel layers. This segmentation into repeatable modular units simplifies the manufacturing process by allowing standardized fabrication steps to be applied iteratively, reducing the cumulative precision requirements compared to creating a monolithic complex structure.
Solution Approach 2:
The patent employs selective doping with different conductivity types (first conductivity type for bit line pillars, second conductivity type for source line pillars) in different spatial locations. This local differentiation of material properties enables precise control of electrical characteristics at specific regions, allowing complex functionality to be achieved through localized modifications rather than global precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D memory design enables efficient programming, erasing, and reading operations, minimizing write interference and sneak voltage issues, thereby enhancing integration and performance.
Implementation Method 1
A 3D memory with a thyristor configuration featuring a stacked structure, annular channel layers, p-type and n-type doped regions
Implementation Method 2
The p-type doped region is disposed in each annular channel layer and adjacent to the first gate. The n-type doped region is disposed in each annular channel layer and adjacent to the second gate.
Data Source
AI summary
Provided are a 3D memory and an operating method thereof. In the 3D memory, a stacked structure includes gate layers and insulating layers alternately stacked. Each gate layer includes first and second gates spaced from each other. Each annular channel layer corresponds to one of the gate layers and is disposed between adjacent insulating layers. A p-type doping region is disposed in each channel layer and adjacent to the first gate. An n-type doped region is disposed in each channel layer and adjacent to the second gate. A source line pillar penetrates through the stacked structure and contacts the n-type doped region. A bit line pillar penetrates through the stack structure and contacts the p-type doped region. A first gate insulation layer is disposed between the first gate and the channel layer. A second gate insulation layer is disposed between the second gate and the channel layer.