3D TMD Transistor Structure for Smaller Footprint and Gate Control
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Solution Overview
Problem
Conventional semiconductor devices have limitations in miniaturization and gate control due to the size and material constraints of transistors, which restricts their performance and efficiency in electronic applications.
Innovation Solution
The use of three-dimensional structures with two-dimensional materials, such as trenches and fins, combined with transition metal dichalcogenides (TMDs) monolayers, allows for the formation of semiconductor devices with a smaller footprint and improved gate control, enabling larger gate widths within a smaller footprint and enhanced transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional transistors are used, then manufacturing is simpler, but device footprint is larger and gate control is weaker
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertical channel transistors with trenches and fins. This dimensional change allows the channel to extend vertically through multiple layers, achieving larger effective gate width and better gate control while reducing the lateral footprint of the device.
Solution Approach 2:
The patent implements nested structures where trenches are formed within fins, and multiple functional layers are stacked vertically. The gate electrode wraps around the vertical channel, and source/drain regions are positioned at different heights, creating a nested configuration that maximizes functionality within a compact footprint.
2Area of stationary object
If transistor size is reduced for miniaturization, then device footprint decreases, but gate control deteriorates
Solution Approach 1:
By moving to vertical channels, the patent maintains strong gate control through the wrapped gate electrode that surrounds the channel in three dimensions, while the reduced lateral footprint is achieved by compressing the structure vertically rather than laterally.
Solution Approach 2:
The patent applies different materials and structures to different regions: high-k dielectric materials in specific layers, metal gates in contact with vertical channels, and selectively doped source/drain regions. This localized optimization ensures effective gate control is maintained in the critical channel region while allowing footprint reduction overall.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor devices with a reduced footprint and improved gate control, leading to more efficient and compact transistor designs, which can enhance the performance of electronic devices.
Implementation Method 1
a heating process is performed in the reaction chamber over the transition metal layer with the chalcogen-containing fluid to transform the transition metal layer into a two-dimensional (2D) material layer
Implementation Method 2
a chalcogen-containing fluid is flowed into the reaction chamber; a heating process is performed in the reaction chamber over the transition metal layer with the chalcogen-containing fluid to transform the transition metal layer into a two-dimensional (2D) material layer
Data Source
AI summary
A method for manufacturing a semiconductor device includes the following steps. A transition metal layer is formed over a substrate in a reaction chamber; a chalcogen-containing fluid is flowed into the reaction chamber; and a heating process is performed in the reaction chamber over the transition metal layer with the chalcogen-containing fluid to transform the transition metal layer into a two-dimensional (2D) material layer over the substrate.