3D Redistribution Trace Layout for Stacked-Die Signal Parity
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining signal parity and timing due to varying trace paths caused by stacking semiconductor dies, leading to desynchronization of signals and processing delays.
Innovation Solution
Implementing three-dimensional trace length matching features, including traces that are neither parallel nor perpendicular to the longitudinal plane, with serpentine shapes and vertical segments, to equalize effective path lengths and ensure parity in signal arrival and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor dies are stacked vertically to reduce device volume, then the volume occupied by semiconductor devices is reduced, but varying trace paths cause signal timing parity to deteriorate
Solution Approach 1:
The patent applies three-dimensional trace routing that extends beyond the traditional two-dimensional plane. Traces are configured to travel through multiple layers and vertical depths within the substrate, utilizing the Z-dimension to create equal-length paths. This dimensional expansion allows signal traces to compensate for path length differences caused by stacked die configurations, maintaining timing parity while preserving the compact vertical architecture.
2Productivity
If bonding sites and rerouting structures are tightly packed to increase capacity within limited area, then the capacity and performance of semiconductor devices are increased, but trace path variations cause signal synchronization to deteriorate
Solution Approach 1:
The patent implements localized trace length matching features at specific critical paths within the redistribution layer. Rather than uniformly adjusting all traces, the design applies targeted serpentine patterns, via structures, and trace routing adjustments only where timing parity is needed. This localized approach maintains high device capacity through tight packing while correcting signal timing discrepancies only in affected regions.
3Device complexity
If conventional two-dimensional trace routing is used in stacked semiconductor devices, then the device structure is simpler, but trace length matching precision deteriorates due to varying path lengths
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional trace routing to achieve precise length matching. By utilizing vertical vias, multi-layer routing, and traces that extend through different depths of the substrate, the design creates equal-length signal paths that compensate for variations introduced by stacked die configurations. This three-dimensional approach provides the precision needed for trace length matching while maintaining manageable structural complexity through systematic routing patterns.
Data Source
AI summary
Semiconductor devices with three-dimensional trace matching features, and related systems and methods, are disclosed herein. In some embodiments, an exemplary semiconductor device includes at least one semiconductor die and a redistribution layer disposed over the at least one semiconductor die and extending across a longitudinal plane. The redistribution layer includes first and second traces each electrically coupled to the at least one semiconductor die. The first trace is disposed in a first travel path included in a first effective path length. The second trace is disposed in a second travel path different from the first travel path. The second the second travel path includes at least one segment at a non-right, non-zero angle such that the at least one segment is neither parallel nor perpendicular to the longitudinal plane. Further, the second travel path is included in a second effective path length equal to the first path length.