3D Redistribution Trace Routing for Signal Timing Parity
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining signal parity and processing timing as they are stacked vertically, due to varying trace paths that lead to desynchronization of signals between components.
Innovation Solution
Implementing three-dimensional trace length matching features, where traces are designed with segments that are neither parallel nor perpendicular to the longitudinal plane, including serpentine paths and vertical orientations, to equalize effective path lengths and ensure signal parity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor dies are stacked vertically to increase capacity and speed, then device capacity and processing speed are improved, but signal timing parity between components deteriorates due to varying trace paths
Solution Approach 1:
The patent introduces three-dimensional trace routing that extends traces vertically through multiple redistribution layers, allowing signal paths to be extended in the Z-dimension rather than only in the planar X-Y dimensions. This dimensional transition enables precise control of trace lengths to achieve timing parity while maintaining compact vertical stacking.
Solution Approach 2:
The patent modifies trace path parameters by introducing serpentine configurations and varying trace orientations (parallel, perpendicular, or at angles to the longitudinal plane) to adjust effective path lengths. These parameter changes allow different signal paths to be equalized in length despite different routing requirements.
2Quantity of substance
If bonding sites and rerouting structures are tightly packed to increase capacity within limited area, then device capacity is improved, but trace path variation increases leading to timing desynchronization
Solution Approach 1:
By utilizing the vertical dimension through multiple redistribution layers, the patent can extend trace paths without increasing planar footprint. This allows tightly packed bonding sites to maintain their high-density arrangement while still achieving sufficient trace length for timing synchronization through vertical routing segments.
Solution Approach 2:
The patent divides trace paths into multiple segments across different redistribution layers, with each segment contributing to the total effective path length. This segmentation allows precise control of individual trace lengths while maintaining compact overall routing, enabling timing parity even with tightly packed sites.
3Quantity of substance
If redistribution layer footprint is reduced to accommodate increased density, then device density is improved, but trace length matching becomes more difficult
Solution Approach 1:
The patent resolves the contradiction by transitioning trace routing from two-dimensional planar paths to three-dimensional paths that utilize vertical spacing between redistribution layers. This allows trace length matching to be achieved within a reduced footprint by extending paths vertically, thereby accommodating increased device density without compromising timing synchronization.
Data Source
AI summary
Semiconductor devices with three-dimensional trace matching features, and related systems and methods, are disclosed herein. In some embodiments, an exemplary semiconductor device includes at least one semiconductor die and a redistribution layer disposed over the at least one semiconductor die and extending across a longitudinal plane. The redistribution layer includes first and second traces each electrically coupled to the at least one semiconductor die. The first trace is disposed in a first travel path included in a first effective path length. The second trace is disposed in a second travel path different from the first travel path. The second the second travel path includes at least one segment at a non-right, non-zero angle such that the at least one segment is neither parallel nor perpendicular to the longitudinal plane. Further, the second travel path is included in a second effective path length equal to the first path length.