3D Transformer Wiring in Semiconductor Chips for High-Voltage Isolation
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving reliable signal transmission between circuits with large potential differences while minimizing electrical noise interference and manufacturing complexity, particularly in maintaining high breakdown voltage and reducing warpage of semiconductor wafers.
Innovation Solution
A three-chip configuration is adopted, where transformers are formed on separate chips from transistors, allowing for simplified manufacturing and improved breakdown voltage without relying on conventional CMOS techniques, with specific wiring and interlayer insulating film designs to enhance electrical isolation and reduce parasitic resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the coil cross-sectional area is increased to reduce parasitic resistance, then signal quality improves, but the device area increases which hinders miniaturization
Solution Approach 1:
The patent transitions from planar 2D coil structures to 3D立体 wiring structures by utilizing multiple wiring layers. The transformer windings are formed by connecting conductors across different wiring layers (first wiring layer, second wiring layer, third wiring layer), creating a three-dimensional coil structure that increases the effective conductor cross-sectional area without expanding the planar device footprint, thereby reducing parasitic resistance while maintaining miniaturization.
Solution Approach 2:
The patent employs composite wiring structures combining different conductor materials and configurations. The transformer windings use conductors from multiple wiring layers connected through via holes, creating a composite 3D structure that effectively increases the conductor cross-sectional area and reduces parasitic resistance without increasing the planar area.
2Reliability
If the breakdown voltage is improved to enable non-contact signal transmission between circuits with large potential differences, then the transformer performance improves, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the insulating structure into multiple segments: first interlayer insulating film between the first and second wiring layers, and second interlayer insulating film between the second and third wiring layers. This segmented approach allows each insulating layer to be optimized for breakdown voltage independently, while the overall structure remains manageable and compatible with standard multi-layer wiring manufacturing processes.
Solution Approach 2:
The patent modifies the thickness parameters of the interlayer insulating films to optimize breakdown voltage. By controlling and adjusting the thickness of the first and second interlayer insulating films, the transformer achieves high breakdown voltage capability for non-contact signal transmission between circuits with large potential differences, while maintaining compatibility with existing manufacturing processes.
3Ease of manufacture
If uniform interlayer insulating film thickness is used to reduce warpage, then manufacturing simplicity improves, but the ability to optimize for parasitic resistance decreases
Solution Approach 1:
The patent applies different thickness values to different interlayer insulating films based on local requirements. The first interlayer insulating film has a first thickness value optimized for reducing parasitic resistance in the lower transformer windings, while the second interlayer insulating film has a second thickness value optimized for the upper transformer windings. This local optimization allows each insulating layer to be tailored for its specific function while maintaining uniform manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of signal transmission by suppressing electrical noise, improves breakdown voltage, and reduces manufacturing complexity and warpage, leading to cost-effective semiconductor devices with improved signal quality.
Implementation Method 1
a pair of inductors coupled inductively
Data Source
AI summary
A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.