3D-Stacked Transistor Barrier Layer for Gate Isolation and Low Resistance
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Solution Overview
Problem
The challenge in 3D-stacked field-effect transistors (3DSFETs) is isolating lower and upper gate structures effectively while maintaining different gate threshold voltages, as existing materials like amorphous silicon lead to voids and increased gate resistance.
Innovation Solution
Implementing a barrier layer made of tantalum nitride or tantalum carbide with higher material density and thinner deposition thickness to isolate the gate structures, preventing etchant attack and reducing gate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If amorphous silicon is used as barrier layer material, then gate structure isolation is achieved, but deposition thickness increases and voids form leading to increased gate resistance
Solution Approach 1:
The patent changes the material parameter from amorphous silicon to crystalline silicon, which fundamentally alters the deposition characteristics. Crystalline silicon enables thinner barrier layers (reducing deposition thickness) while maintaining effective isolation between gate structures, thereby resolving the contradiction between isolation reliability and thickness control
Solution Approach 2:
The patent employs a composite barrier layer structure combining crystalline silicon with other materials optimized for specific functions. This composite approach allows the barrier layer to achieve both thin deposition thickness and effective void prevention, simultaneously improving isolation reliability while reducing the thickness parameter
2Reliability
If amorphous silicon is used as barrier layer material, then gate structure isolation is achieved, but voids form leading to increased gate resistance
Solution Approach 1:
Changing from amorphous to crystalline silicon alters the material's structural parameters, eliminating void formation during deposition. This parameter change directly reduces the harmful factor of gate resistance while preserving the isolation function
Solution Approach 2:
The patent converts the potential harm of void formation into a benefit by using crystalline silicon's superior deposition properties. The crystalline structure inherently prevents void formation, transforming what would be a harmful defect into a reliable isolation mechanism with lower gate resistance
3Object-affected harmful factors
If barrier layer thickness is reduced, then gate resistance is lowered, but isolation effectiveness may be compromised
Solution Approach 1:
The patent changes the material parameter to crystalline silicon, which provides superior isolation effectiveness at reduced thickness compared to amorphous silicon. This parameter change enables thinner barrier layers that maintain or improve isolation effectiveness while reducing gate resistance
Solution Approach 2:
The patent optimizes the local quality of the barrier layer by using crystalline silicon with specific structural properties tailored for thin-film applications. This local optimization allows the barrier layer to achieve effective isolation at minimal thickness, simultaneously reducing gate resistance and maintaining isolation reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The tantalum nitride barrier layer effectively isolates gate structures, maintaining distinct gate threshold voltages and reducing gate resistance, enhancing the performance of 3DSFET devices.
Implementation Method 1
the lower gate structure is isolated from the upper gate structure by a barrier layer having a smaller deposition thickness
Implementation Method 2
at least one of the 1st channel structure and the 2nd channel structure may include a high-k dielectric material diffused therein
Data Source
AI summary
Provided is a three-dimensionally-stacked field-effect transistor (3DSFET) device including a plurality of 3DSFETs on a single substrate, wherein each of the 3DSFET includes: a 1st channel structure surrounded by a 1st gate structure; and a 2nd channel structure surrounded by a 2nd gate structure, the 2nd channel structure provided on the 1st channel structure, and wherein, in at least one of the 3DSFETs, the 1st gate structure is isolated from the 2nd gate structure through a barrier layer including a dielectric material comprising tantalum.