3D Transistor Gate Metal with Dielectric Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In advanced CMOS technologies, three-dimensional (3D) parasitic capacitances between gate metal and source/drain contacts in 3D transistors adversely impact chip performance, particularly in integrated circuits with FinFETs, due to the coupling of gate metal across isolation regions.
Innovation Solution
Replacing a portion of the gate metal over the isolation region with a dielectric material, such as silicon nitride, to reduce coupling capacitance, and optionally adding a conducting layer with higher conductivity to improve gate conductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If gate metal is extended across the isolation region to connect transistors, then electrical connectivity is achieved, but parasitic capacitance increases
Solution Approach 1:
The gate structure is segmented into two distinct portions: a first gate portion made of gate metal extending over the diffusion region, and a second gate portion made of conductive material extending over the isolation region. This segmentation allows each portion to be optimized for its specific function - the metal portion for electrical connectivity and the conductive material portion for minimizing parasitic capacitance.
Solution Approach 2:
Different materials are used in different spatial locations of the gate structure. The gate metal is placed locally over the diffusion region where high conductivity is needed, while conductive material with lower capacitance characteristics is placed locally over the isolation region where parasitic capacitance must be minimized. This local differentiation resolves the contradiction between connectivity and parasitic capacitance.
2Reliability
If gate metal thickness is increased to improve gate conductance, then electrical performance improves, but parasitic capacitance increases
Solution Approach 1:
The gate structure employs different material compositions in different regions to simultaneously achieve high conductance and low parasitic capacitance. The first gate portion over the diffusion region uses gate metal optimized for conductance, while the second gate portion over the isolation region uses conductive material optimized for low capacitance, resolving the trade-off between conductance and parasitic capacitance.
Solution Approach 2:
The gate structure is formed as a composite of two different materials: gate metal and conductive material. Each material contributes its superior properties to the overall gate structure - the metal provides high conductivity where needed, while the conductive material provides low capacitance characteristics in the isolation region, achieving both high gate conductance and low parasitic capacitance simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate-to-contact parasitic capacitance by approximately 70% and improves chip performance by 5-10% by minimizing electrical coupling and enhancing conductance.
Implementation Method 1
reduces gate to contact parasitic capacitance in integrated circuits having three-dimensional (3D) transistors
Data Source
AI summary
An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.