3D Transistor LDD Region Oxidation for GIDL Reduction
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Solution Overview
Problem
Current semiconductor integration circuit devices face limitations in achieving high integration density and reducing gate-induced drain leakage (GIDL) in three-dimensional (3D) transistors, which are essential for next-generation memory devices with high capacity, speed, and low power consumption.
Innovation Solution
A 3D semiconductor device structure is developed, featuring a source, channel layer, lightly doped drain (LDD) region, and gate insulating layer, where the LDD region is formed of a semiconductor material with a higher oxidation rate than the channel and drain materials, and a gate insulating layer is formed on the outer circumferences to reduce electric field concentration and prevent GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a high voltage is supplied to the gate of the 3D transistor, then the transistor can be operated, but a relatively high electric field is applied to the LDD overlapping the gate, causing gate-induced drain leakage (GIDL)
Solution Approach 1:
The patent applies local quality by forming a gate insulating layer with non-uniform thickness, where the thickness is greater at the LDD region overlapping the gate compared to other regions. This localized thickness variation reduces the electric field concentration specifically at the LDD-gate overlap area, thereby reducing GIDL while maintaining normal transistor operation at high voltage
Solution Approach 2:
The patent changes the physical parameter of the gate insulating layer thickness to resolve the contradiction. By increasing the gate insulating layer thickness at critical regions (LDD-gate overlap), the electric field is reduced, which suppresses GIDL while allowing the transistor to operate at high voltage for improved performance and integration density
2Productivity
If integration density is improved by using 3D transistor structure, then more memory cells can be integrated, but GIDL increases due to electric field concentration at LDD
Solution Approach 1:
The patent maintains the 3D transistor structure for high integration density while applying local quality enhancement by forming a thicker gate insulating layer specifically at the LDD region. This localized modification reduces GIDL at the critical overlap area without compromising the overall 3D structure and integration density benefits
3Volume of moving object
If a thin gate insulating layer is used in 3D transistor, then device size is reduced, but electric field concentration at LDD increases causing GIDL
Solution Approach 1:
The patent uses a thin gate insulating layer overall to maintain small device size, but applies local quality by increasing the thickness specifically at the LDD region overlapping the gate. This creates a non-uniform gate insulating layer that keeps the device compact while reducing GIDL at the critical area through localized thickness enhancement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure enhances integration density and reduces GIDL, enabling the development of high-capacity, high-speed, and low-power memory devices by effectively managing the electric field and leakage current.
Implementation Method 1
a lightly doped drain (LDD) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material
Data Source
AI summary
A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The method may include forming a source on a semiconductor substrate, sequentially forming a first semiconductor layer formed of a first material, a second semiconductor layer formed of a second material having a higher oxidation rate than that of the first material, and a third semiconductor layer formed of the first material on the source; patterning the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; forming a lightly doped drain (LDD) region in the second semiconductor layer and a drain in the third semiconductor layer; oxidizing outer circumferences of the first semiconductor layer, the LDD region and the drain region to form a gate insulating layer; forming a gate on an outer circumference of the gate insulating layer to overlap the first semiconductor layer and a portion of the LDD region; foaming a heating electrode on the drain; and forming a variable resistance layer on the heating electrode.