3D Transistor Structure for Low Parasitic Capacitance
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Solution Overview
Problem
Current transistors face challenges in achieving miniaturization, low parasitic capacitance, high frequency characteristics, and stable electrical performance due to limitations in design and materials used.
Innovation Solution
A semiconductor device structure is developed with a specific configuration of conductors, insulators, and a semiconductor over a substrate, where the semiconductor overlaps with multiple conductors, and the insulators are strategically positioned to reduce parasitic capacitance and enhance electrical characteristics, including a surrounded channel structure to increase on-state current and decrease off-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the transistor size is reduced to achieve miniaturization, then the device area is reduced, but the parasitic capacitance increases and electrical characteristics deteriorate
Solution Approach 1:
The invention transitions from a planar transistor structure to a three-dimensional structure by forming the semiconductor layer to overlap with both the gate electrode and the source/drain electrodes in the vertical dimension. This dimensional change allows the channel region to extend over multiple electrodes, reducing parasitic capacitance while maintaining compact footprint area.
Solution Approach 2:
The semiconductor layer is segmented into distinct regions: a first region overlapping the gate electrode, a second region overlapping the source/drain electrode, and a third region connecting them. This segmentation allows independent optimization of each region's function while maintaining overall electrical performance.
2Device complexity
If conventional transistor structures are used, then the design is simple, but the frequency characteristics and speed performance are limited
Solution Approach 1:
By extending the semiconductor layer vertically to overlap with multiple electrodes (gate, source, and drain), the invention creates a three-dimensional current path that reduces parasitic capacitance and improves frequency characteristics without significantly increasing planar footprint.
Solution Approach 2:
The semiconductor layer is positioned to be nested over multiple electrode structures, with the channel formation region extending over the gate electrode and the source/drain regions overlapping with the source/drain electrodes, creating a nested configuration that maximizes electrical performance within compact space.
3Speed
If the transistor channel length is reduced to increase speed, then the operating frequency increases, but the off-state current increases and leakage worsens
Solution Approach 1:
The semiconductor layer is designed with different functional regions having distinct properties: the first region over the gate electrode forms the channel with specific thickness for high mobility, while the second region over the source/drain electrode is configured to control carrier injection and extraction, allowing independent optimization of speed and leakage characteristics.
Data Source
AI summary
A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.