3D Transistor Stack Spacers With Low-k Sections for Capacitance Reduction
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Solution Overview
Problem
The formation of high aspect-ratio gates in stacked transistors of three-dimensional (3D) transistor structures poses challenges for implementing effective gate-metal processes, leading to difficulties in reducing capacitance.
Innovation Solution
The use of insulating spacers with a lower dielectric constant than silicon nitride, featuring an inner portion made of oxide or vacancy, is introduced to reduce capacitance in 3D transistor structures. These spacers are strategically placed on the sidewalls of gates between semiconductor channel layers, optimizing the dielectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional insulating spacers are used in stacked transistor structures, then the structure is simple to manufacture, but the capacitance between semiconductor channel layers and gates is undesirably high
Solution Approach 1:
The insulating spacer is divided into multiple portions with different dielectric constants placed at different locations. The first portion (outer portion) has a higher dielectric constant material closer to the gate, while the second portion (inner portion) has a lower dielectric constant material closer to the semiconductor channel layer. This local differentiation of material properties allows optimization of capacitance reduction while maintaining manufacturability.
Solution Approach 2:
The insulating spacer is formed as a composite structure combining multiple insulating materials with different dielectric constants. The first insulating material (higher dielectric constant) and second insulating material (lower dielectric constant) are combined in a single spacer structure, creating a composite that simultaneously provides mechanical support and optimized electrical characteristics to reduce capacitance.
2Quantity of substance
If high aspect-ratio gates are used in 3D transistor structures, then transistor density is increased, but gate-metal processes become difficult and complicated
Solution Approach 1:
The multi-portion insulating spacer acts as an intermediary structure between the gate and the semiconductor channel layer. By providing a tailored dielectric environment with different material portions at different distances from the gate, it facilitates the gate-metal process by reducing capacitance effects that would otherwise complicate high aspect-ratio gate fabrication in dense 3D transistor structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of insulating spacers with a lower dielectric constant effectively reduces capacitance, improving the performance of 3D transistor structures by enhancing the dielectric properties and facilitating more efficient gate-metal processes.
Implementation Method 1
the insulating spacer may include: a first portion on a sidewall of the gate; and a second portion that is spaced apart from the sidewall of the gate by the first portion, and that has a lower dielectric constant than the first portion
Data Source
AI summary
Transistor devices are provided. A transistor device includes a substrate and a transistor stack including first and second transistors on the substrate. The first transistor or the second transistor includes a plurality of semiconductor channel layers, a gate on the plurality of semiconductor channel layers, and an insulating spacer that is on a sidewall of the gate and between the plurality of semiconductor channel layers. Moreover, the insulating spacer includes: a first portion on a sidewall of the gate; and a second portion that is spaced apart from the sidewall of the gate by the first portion, and that has a lower dielectric constant than the first portion. Related methods of forming transistor devices are also provided.