3D Transistor Vertically Recessed Channel Fabrication
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Solution Overview
Problem
Traditional planar transistors face physical limits as device dimensions shrink, necessitating the development of new 3D transistor structures and manufacturing methods to maintain functionality and efficiency.
Innovation Solution
The fabrication of 3D transistors with vertically recessed channel regions, where a semiconductor fin is etched to form a vertically recessed channel and source/drain regions, allowing for a gate stack to be formed over the channel, enabling better gate control and reducing the need for raised epitaxial source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional planar transistor structures are used, then manufacturing processes are simpler, but device dimensions cannot be scaled down further due to physical limits
Solution Approach 1:
The patent transitions from traditional planar (2D) transistor structures to three-dimensional FinFET structures with vertically recessed channels. This dimensional change allows continued scaling of device dimensions by utilizing the vertical dimension for gate control, overcoming the physical limits of planar transistors while maintaining manufacturability through established etching and deposition processes.
2Reliability
If vertically recessed channel regions are formed by etching, then gate control is improved, but fabrication process complexity increases
Solution Approach 1:
The patent employs preliminary actions by first forming sacrificial mandrels and isolation structures before creating the vertically recessed channels. The gate stack is formed after the recesses are etched, allowing the gate to conformally coat the vertical walls. This sequence of preliminary actions simplifies the overall fabrication by breaking down the complex 3D structure formation into manageable steps using standard semiconductor processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for smaller channel dimensions, reduced contact resistance, and simpler fabrication processes, enabling higher integration density and cost-effectiveness without stringent lithography requirements.
Implementation Method 1
A vertically recessed channel region is formed by etching from a sidewall of the fin
Data Source
AI summary
A method includes providing a substrate having a mesa, forming a first opening in the mesa, the first opening being surrounded by first inner sidewalls of the mesa exposed by the first opening. The method further includes etching from a first one of the first inner sidewalls of the mesa to form a first vertical recess, the first vertical recess having a wide end and a narrow end, with the narrow end defining a first vertically recessed channel region, and forming a first gate structure over the first vertically recessed channel region.