3D Single-Crystal Transistor Stacks With Self-Aligned Interconnects
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Solution Overview
Problem
Current 3D semiconductor chip technologies face challenges in constructing transistors in three dimensions due to high temperature requirements that damage wiring layers, limited connectivity between stacked wafers, and misalignment issues, leading to low contact density and performance degradation.
Innovation Solution
The method involves forming single crystal transistors at lower temperatures using alignment marks and self-aligned lithography, etching steps, and oxide-to-oxide bonding to create high-density connections between layers, allowing for the construction of 3D semiconductor devices with improved alignment and reduced misalignment errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are constructed at high temperatures (>700°C) to achieve proper transistor formation, then transistor performance is improved, but wiring layers are damaged due to temperatures exceeding their tolerance (>400°C)
Solution Approach 1:
The patent divides the transistor construction process into multiple stages with different temperature requirements. The first transistor layer is formed at high temperature (>700°C) on the substrate, then a first wiring layer is formed at lower temperature. Subsequently, additional transistor layers are formed at controlled temperatures that do not exceed the wiring layer's thermal tolerance, achieving both high-performance transistors and intact wiring layers through temporal and spatial separation of processing steps.
Solution Approach 2:
The patent employs parameter changes by adjusting processing temperatures for different layers and stages. Specifically, the substrate temperature is dynamically controlled: high temperature for the first transistor layer, then reduced for wiring layer formation, and subsequently optimized for additional transistor layers. This parameter modulation enables compatibility between high-performance transistor fabrication and heat-sensitive wiring layer preservation.
2Ease of manufacture
If conventional lithography and alignment methods are used for stacking wafers, then manufacturing simplicity is maintained, but misalignment errors occur leading to low contact density
Solution Approach 1:
The patent implements preliminary action by pre-forming alignment marks on the substrate before wafer stacking, and pre-defining contact hole patterns with enhanced alignment features. These preparatory structures enable subsequent layers to be accurately positioned during stacking, achieving high alignment precision without complicating the overall manufacturing process. The alignment marks serve as reference features that guide precise layer registration.
Solution Approach 2:
The patent replaces conventional mechanical alignment methods with lithography-based alignment using alignment marks and self-aligned lithography techniques. Instead of relying solely on mechanical positioning systems, the invention uses light-based lithographic patterns and etched alignment features to define precise layer registrations, achieving sub-micron alignment accuracy while maintaining manufacturing simplicity through standard lithographic processes.
3Quantity of substance
If the number of contact holes is increased to improve connectivity between layers, then contact density improves, but manufacturing complexity and etch process difficulty increase
Solution Approach 1:
The patent applies the nested doll principle by forming contact holes through multiple etch steps where each subsequent etch penetrates through previously formed layers to reach deeper targets. The etch processes are nested sequentially: first etch creates holes through the first transistor layer, second etch extends through the wiring layer, and third etch reaches the substrate or lower layers. This nested approach enables high contact density with systematic, manageable etch processes rather than attempting to create all contacts in a single complex step.
Solution Approach 2:
The patent uses preliminary action by pre-defining contact hole patterns and positions through lithography before etching, and by pre-forming mandrels or spacer structures that guide the etch process. These preparatory features enable precise control of contact hole locations and dimensions, achieving high contact density while simplifying the etch process through predetermined patterns rather than free-form drilling or complex real-time control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of 3D semiconductor devices with high-density connections and reduced misalignment, enhancing performance and reliability by maintaining the integrity of both transistors and wiring layers.
Implementation Method 1
oxide-to-oxide bonding to create high-density connections between layers
Data Source
AI summary
A semiconductor device including: a first level including a plurality of first metal layers; a second level overlaying the first level, where the second level includes at least one single-crystal silicon layer and a plurality of transistors, where each of the plurality of transistors includes a single-crystal channel, where the second level includes a plurality of second metal layers which includes interconnections between the plurality of transistors, the second level is overlaid by an isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where at least one of the plurality of transistors includes a second single-crystal channel overlaying a first single-crystal channel, where each of at least one of the plurality of transistors includes at least a two sided gate, where the first single-crystal channel is self-aligned to the second single-crystal channel being processed following a same lithography step.