3D Transistor Stack SRAM Cell via Horizontal S/D Connections
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Solution Overview
Problem
The challenge in semiconductor device fabrication is the limitation of transistor density scaling due to manufacturing variability and electrostatic device limitations in two-dimensional circuits, which can be overcome by transitioning to three-dimensional (3D) semiconductor circuits where transistors are stacked vertically, but this requires innovative methods for connecting and integrating transistors effectively.
Innovation Solution
The method involves forming stacks of transistor structures with horizontal channels and source/drain (S/D) regions on a substrate, where the S/D regions of adjacent stacks are connected using epitaxially grown material or metal to form a connecting structure, allowing for vertical stacking and reduced layout size, enabling 3D logic integration and SRAM cell formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional transistor scaling is continued to increase transistor density, then transistor density per unit area improves, but manufacturing variability and electrostatic device limitations worsen
Solution Approach 1:
The patent transitions from two-dimensional transistor scaling to three-dimensional vertical stacking of transistors. Multiple transistor layers are stacked vertically with source/drain regions connected through epitaxially grown connecting structures, enabling increased transistor density while maintaining electrostatic performance and reducing manufacturing variability associated with 2D scaling.
2Quantity of substance
If three-dimensional vertical transistor stacking is implemented to overcome scaling limits, then transistor density improves, but device complexity and integration difficulty worsen
Solution Approach 1:
The patent merges multiple transistor layers vertically into compact stacks, with source/drain regions from different layers connected through epitaxially grown connecting structures. This combining approach achieves high transistor density while simplifying the overall device structure compared to traditional 2D layouts, and enables standard CMOS compatibility.
Solution Approach 2:
The epitaxial growth process automatically forms connecting structures between source/drain regions of adjacent transistor layers, enabling self-aligned connections without requiring additional complex lithography or patterning steps. This self-service mechanism reduces integration complexity.
3Quantity of substance
If wire pitch is reduced to increase transistor wiring density, then transistor wiring density improves, but resistance and capacitance increase
Solution Approach 1:
The patent moves interconnect routing from the planar 2D domain to the 3D vertical domain by stacking transistors vertically. This dimensional transition allows wiring to proceed vertically through the stack, dramatically reducing wire pitch and enabling higher wiring density while maintaining acceptable resistance and capacitance characteristics through optimized vertical interconnect design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased transistor density, reduced connection space, and simplified layout, making 3D logic integration feasible, allowing for the use of all transistors in logic cells and memory, including SRAM, with reduced layout size and the integration of buried power rails.
Implementation Method 1
A first stack of first transistor structures and a second stack of second transistor structures are connected by epitaxially grown material
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a first stack of first transistor structures on a substrate, and forming a second stack of second transistor structures on the substrate adjacent to the first stack. The second stack is formed adjacent to the first stack such that stacked S/D regions at an end of the first stack are facing respective stacked S/D regions at an end of the second stack. A first pair of facing S/D regions of the first and second stack is connected by forming a connecting structure that extends in the horizontal direction to physically connect the first pair of facing S/D regions to each other. A second pair of facing S/D regions of the first and second stack is maintained as a separated pair of facing S/D regions which are physically separated from one another. First and second metal interconnect structures are connected to respective S/D regions in the second pair of facing S/D regions.