3D Transistor Stack with Dynamic Threshold Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing microelectronic devices with transistors integrated in 3D and distributed over several levels face challenges in reducing integration density and power consumption while maintaining electrical performance and operating speed, particularly due to limitations in dynamically modifying the threshold voltage of transistors.
Innovation Solution
A microelectronic device with superimposed transistors separated by an insulating zone of varying composition and thickness, allowing for dynamic modulation of the threshold voltage of upper transistors by coupling with lower transistors through a specific dielectric region, while preventing parasitic coupling between access zones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are integrated in 3 dimensions and distributed over several levels, then integration density is improved, but noise between different levels increases and parasitic coupling occurs
Solution Approach 1:
The insulating zone is segmented into multiple layers with different dielectric materials, where the first insulating layer has higher permittivity than the second insulating layer. This segmentation allows selective coupling between transistor gates while reducing parasitic effects, resolving the contradiction between high integration density and noise reduction.
Solution Approach 2:
Different regions of the insulating zone have different dielectric properties - the first insulating layer provides strong coupling in specific areas while the second layer provides isolation in other areas. This local differentiation enables simultaneous achievement of coupling where needed and noise reduction where not needed.
2Use of energy by moving object
If supply voltage is reduced to decrease power consumption, then energy consumption is improved, but operating speed and electrical performance deteriorate
Solution Approach 1:
The invention dynamically changes the threshold voltage parameter of transistors by utilizing capacitive coupling through the multi-layer insulating structure. By adjusting the voltage on lower-level transistor gates, the threshold voltage of upper-level transistors is modulated, enabling operation at lower supply voltages without sacrificing speed or performance.
3Speed
If threshold voltage is reduced to improve operating speed, then speed is improved, but static power consumption increases
Solution Approach 1:
The threshold voltage is made dynamic rather than fixed, allowing it to be adjusted based on operational requirements. Through capacitive coupling via the insulating zone, the threshold voltage can be temporarily reduced during active operations to boost speed, then restored to higher values during idle periods to minimize static power consumption.
4Adaptability or versatility
If ground plane structure is used to modify threshold voltage, then threshold voltage control is improved, but capacitance between source/drain and substrate increases causing signal propagation degradation
Solution Approach 1:
The multi-layer insulating zone acts as an intermediary structure between the substrate and transistor source/drain regions. By using layers with different permittivities, it provides controlled capacitive coupling for threshold voltage modulation while maintaining sufficient isolation to prevent excessive capacitance that would degrade signal propagation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient variation of the threshold voltage of upper transistors by varying the gate potential of lower transistors, improving electrical performance and reducing power consumption while maintaining high integration density.
Implementation Method 1
allowing for dynamic modulation of the threshold voltage of upper transistors by coupling with lower transistors through a specific dielectric region
Implementation Method 2
the first transistor and the second transistor being separated by an insulating zone of varying composition and thickness
Data Source
AI summary
A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.