3D Vertical Transistor Stacking for Leakage Current Control
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Solution Overview
Problem
As semiconductor devices approach single-digit nanometer fabrication nodes, fabricators face challenges with leakage currents and short-channel effects due to the shrinking space between active features, which hinders further scaling and increases complexity in microelectronic device manufacturing.
Innovation Solution
The implementation of three-dimensional (3D) semiconductor circuits where transistors are stacked vertically, utilizing chemical compounds like silicide and germanicide regions formed between metals and semiconductors, such as silicon and germanium, to improve electrical properties and reduce leakage currents and short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 2D circuits are scaled to increase transistor density, then the number of transistors per unit area increases, but leakage currents and short-channel effects worsen
Solution Approach 1:
The patent transitions from 2D planar transistor layouts to 3D vertically stacked transistor configurations. Multiple transistor layers are stacked along the vertical dimension, allowing increased transistor density without further shrinking lateral feature sizes. This dimensional transition maintains adequate spacing between transistors while achieving higher density, thereby reducing leakage currents and short-channel effects.
2Productivity
If feature sizes are reduced to single-digit nanometers, then transistor scaling is achieved, but manufacturing complexity increases
Solution Approach 1:
By stacking transistors vertically, the patent achieves transistor scaling without requiring further reduction of lateral feature sizes to single-digit nanometers. This approach uses the vertical dimension for scaling while maintaining larger, more manufacturable lateral dimensions, thereby reducing fabrication process complexity.
3Productivity
If space between active features is reduced, then circuit density increases, but short-channel effects become more pronounced
Solution Approach 1:
The patent places multiple transistor layers at different vertical heights, allowing circuit density to increase through vertical stacking rather than lateral compression. This maintains adequate horizontal spacing between active features, preventing short-channel effects while achieving high circuit density.
Solution Approach 2:
The patent implements nested transistor structures where multiple transistor layers are stacked one above another in a vertical column. Each transistor layer is nested within the same lateral footprint but at different vertical levels, achieving high density without reducing the spacing between corresponding features in adjacent layers.
4Reliability
If silicide and germanicide regions are formed through annealing, then electrical conductivity is enhanced, but process temperature requirements increase
Solution Approach 1:
The patent forms silicide and germanicide regions by controlling the chemical reaction between metal layers and semiconductor materials during annealing. By adjusting annealing parameters such as temperature, time, and atmosphere, the patent achieves desired electrical conductivity enhancements while managing the thermal budget of the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved scaling with increased circuits per unit area, enhanced electrical properties, and reduced leakage currents, allowing for higher density and performance in microelectronic devices while maintaining effective electrical conductivity.
Implementation Method 1
utilizing chemical compounds formed between metals and semiconductors via annealing, such as silicide and germanicide regions
Data Source
AI summary
The solution provides a device formed in a layer stack that includes a source contact layer and a gate contact layer with a first insulation between the gate contact layer and the source contact layer and a drain contact layer with a second insulation between the gate contact layer and the drain contact layer. The layer stack can include a device region orthogonal to a plane defined by a surface of at least one of the layers of the stack. The device region includes a source and a drain separated by a channel at least partially surrounded by a gate dielectric interposed between the gate contact layer and the channel and a first region that can include a silicide or a germanicide at a first end proximal to the source and a second region that can include the silicide or the germanicide at a second end proximal to the drain.