3D Single-Crystal Transistor Stacking With Sub-40 Nm Alignment
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Solution Overview
Problem
Current 3D semiconductor chip stacking technologies face challenges in constructing transistors above wiring layers without damaging them, due to temperature compatibility issues, leading to low connectivity and high power consumption, and existing solutions suffer from misalignment and defect density problems.
Innovation Solution
The method involves forming single crystal transistors with alignment marks, using lithographic and etch steps to create memory cells across multiple layers with oxide-to-oxide bonding, and employing layer transfer techniques to achieve high-density connections and reliable bonding without exceeding 400°C processing temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are constructed above wiring layers using high temperature processing (>700°C), then transistor performance and density improve, but the bottom wiring layer gets damaged
Solution Approach 1:
The patent divides the transistor construction process into separate temperature stages: low-temperature wiring formation (<400°C) followed by high-temperature transistor processing (>700°C) on the same monolithic structure. This segmentation allows each component to be processed at its optimal temperature without damaging other components.
Solution Approach 2:
The wiring layers are constructed first at low temperatures before the transistor layers are formed at high temperatures. This preliminary action ensures that the temperature-sensitive wiring is already in place and protected from subsequent high-temperature processing that occurs during transistor fabrication.
2Speed
If 3D stacking is implemented to reduce wire lengths, then wiring delay decreases, but alignment precision and defect density increase
Solution Approach 1:
The patent merges multiple transistor layers and wiring layers into a single monolithic 3D integrated circuit structure formed through sequential monolithic integration. This combining approach maintains precise alignment between layers while enabling 3D stacking for reduced wire lengths and improved signal transmission speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the construction of 3D semiconductor devices with high-density connections and improved transistor performance by aligning transistors with less than 40nm error, reducing misalignment issues and defect density, while maintaining reliable bonding and power efficiency.
Implementation Method 1
employing layer transfer techniques to achieve high-density connections and reliable bonding without exceeding 400°C processing temperatures
Data Source
AI summary
A semiconductor device including: a plurality of transistors, where at least one of the transistors includes a first single crystal source, channel, and drain, where at least one of the transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the transistors includes a fourth single crystal source, channel, and drain, where the fourth single crystal source, channel, and drain is disposed above the third single crystal source, channel, and drain, and where the fourth drain is aligned to the first drain with less than 40 nm misalignment.