3D Stacked Semiconductor Transistors via Dielectric Wafer Bonding
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Solution Overview
Problem
The increased density of IC devices, such as transistors, has led to processing complexity due to decreased feature sizes, necessitating innovative manufacturing methods to enhance efficiency and reduce complexity.
Innovation Solution
A method involving the formation of an epitaxial layer on a first substrate, followed by dielectric layer bonding and separation, combined with transistor formation on both substrates, allows for flexible material choices and reduced device dimensions through 3D stacking of transistors with varying gate lengths and materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more aggressive design rules are implemented to increase IC device density, then the density of transistors is improved, but the complexity of processing semiconductor devices increases
Solution Approach 1:
The patent divides the semiconductor manufacturing process into separate stages by forming transistors on different substrates (first substrate with initial transistors, second substrate with subsequent transistors). This segmentation allows each substrate to be processed independently with optimized design rules, reducing overall processing complexity while maintaining high device density through 3D stacking of multiple transistor layers.
2Quantity of substance
If feature sizes are decreased to increase device density, then the density of IC devices is improved, but the complexity of processing semiconductor devices increases
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical stacking by forming transistor layers on both the first and second substrates and bonding them together. This dimensional change allows device density to increase vertically rather than requiring continuous reduction of feature sizes, thereby reducing processing complexity associated with nanoscale fabrication.
3Length of moving object
If 3D stacking of transistors is implemented, then device dimensions are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming complete transistor structures on the first substrate before bonding to the second substrate. This includes forming source/drain regions, gate electrodes, and interconnect structures in advance. The preliminary fabrication on separate substrates simplifies the overall manufacturing process compared to attempting to form all structures in a single complex 3D sequence.
Solution Approach 2:
The patent uses dielectric layers and bonding interfaces as intermediaries between the first and second substrate transistor layers. These intermediary structures facilitate the bonding process and provide mechanical and electrical coupling between the stacked transistor layers, enabling 3D integration while managing manufacturing complexity through standardized interface designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces device dimensions and processing complexity by enabling flexible material choices and 3D transistor stacking, enhancing manufacturing efficiency and device performance.
Implementation Method 1
an epitaxial layer is grown on a first region of a first wafer
Implementation Method 2
a first dielectric layer is formed over the epitaxial layer and the second region, and a second dielectric layer is formed over the second transistor, and the first and second dielectric layers are bonded
Data Source
AI summary
A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.