3D Trench Capacitor Stacking to Avoid Deep-Trench Void Formation
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Solution Overview
Problem
Semiconductor manufacturing processes limit the depth of trench segments in integrated passive devices (IPDs), leading to reduced capacitance density due to trench necking and void formation at high aspect ratios, which restricts the size reduction of IPDs.
Innovation Solution
A three-dimensional (3D) trench capacitor design is implemented, utilizing hybrid bonding and through substrate vias (TSVs) to couple trench capacitors across multiple device layers, increasing capacitance density by summing individual capacitances while maintaining a small footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If trench depth is increased to improve capacitance density, then capacitance density is improved, but trench necking and void formation occur due to high aspect ratios
Solution Approach 1:
The capacitor structure is divided into multiple trench segments stacked vertically across different device layers. Each segment is formed within manufacturing depth limits, avoiding high aspect ratios and associated defects while achieving high overall capacitance through the stacked configuration of multiple segments.
Solution Approach 2:
The capacitor structure transitions from a traditional single-layer 2D configuration to a 3D stacked configuration spanning multiple device layers. This dimensional transition allows capacitance accumulation in the vertical direction without requiring excessive trench depth in any single layer, thereby avoiding trench necking and void formation.
2Productivity
If IPD size is reduced to improve integration density, then functional density is improved, but capacitance density is reduced due to manufacturing process limits
Solution Approach 1:
The capacitor structure transitions from a traditional single-layer 2D configuration to a 3D stacked configuration spanning multiple device layers. This dimensional transition allows capacitance accumulation in the vertical direction without requiring excessive trench depth in any single layer, thereby avoiding trench necking and void formation.
Solution Approach 2:
Multiple trench segments are nested vertically within the three-dimensional structure, with each segment contained within a specific device layer. This nested arrangement maximizes capacitance within the available vertical space while maintaining compatibility with standard manufacturing process depth limits.
3Quantity of substance
If trench aspect ratio is increased to improve capacitance per footprint area, then capacitance density is improved, but void formation and manufacturing challenges increase
Solution Approach 1:
The capacitor structure is divided into multiple trench segments stacked vertically across different device layers. Each segment is formed within manufacturing depth limits, avoiding high aspect ratios and associated defects while achieving high overall capacitance through the stacked configuration of multiple segments.
Solution Approach 2:
The capacitor structure transitions from a traditional single-layer 2D configuration to a 3D stacked configuration spanning multiple device layers. This dimensional transition allows capacitance accumulation in the vertical direction without requiring excessive trench depth in any single layer, thereby avoiding trench necking and void formation.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.