3D Trench Semiconductor Structure for Crack Blocking in Thick Dielectrics
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Solution Overview
Problem
Existing silicon processing technology for high-voltage applications is incompatible with the dielectric thickness required, leading to mechanical stress, wafer warpage, and increased probability of defects such as dielectric cracking or delamination in 3D capacitor structures.
Innovation Solution
A semiconductor structure with a substrate featuring a functional circuit structure surrounded by a first three-dimensional structure comprising continuous trenches that extend into the substrate, reducing mechanical stress and preventing cracks from propagating into the functional circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric layer thickness is increased to sustain the operating electrical field in high-voltage applications, then the electrical field margin is improved, but the mechanical stress increases and wafer warpage occurs
Solution Approach 1:
The patent segments the wafer surface into three-dimensional structures (protrusions and recesses) that distribute the mechanical stress locally, allowing the use of thicker dielectric layers without causing global wafer warpage. The 3D geometry creates stress distribution zones that prevent stress concentration.
Solution Approach 2:
The patent transitions from a planar (2D) wafer surface to a three-dimensional surface with protrusions and recesses. This dimensional change allows the dielectric layer to be deposited on a 3D surface, creating stress relief through the vertical dimension while maintaining electrical field integrity.
2Adaptability or versatility
If the dielectric layer thickness is increased beyond 0.7 microns, then high-voltage application compatibility is improved, but the probability of dielectric cracking or delamination increases
Solution Approach 1:
The patent applies a crack-blocking layer (such as a sacrificial layer or stress-relief layer) before depositing the thick dielectric layer. This pre-deposited layer acts as a cushion that prevents crack propagation and delamination, allowing the subsequent dielectric layer to be deposited at greater thickness without defects.
Solution Approach 2:
The patent changes the physical and chemical parameters of the interface between the substrate and dielectric layer by introducing intermediate layers or modifying surface properties. This parameter change reduces adhesion issues and stress concentration, enabling thicker dielectric layers without cracking or delamination.
3Area of stationary object
If full wafer deposition is used for the dielectric layer, then the dielectric coverage is improved, but mechanical stress in 2D areas increases leading to cracks and delamination
Solution Approach 1:
The patent applies different local qualities to different regions of the wafer. The 3D structures (protrusions and recesses) are designed with specific geometries that locally manage stress, while the 2D areas are protected by crack-blocking structures. This local differentiation allows full wafer deposition to proceed without causing stress-induced defects in the 2D regions.
Data Source
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AI summary
A semi-conductor structure with a crack-blocking three-dimensional structure is described. The semiconductor structure comprises a substrate (402); a functional circuit structure (404) disposed in an area of the substrate; and a three-dimensional structure (406) comprising at least one continuous trench (410) that extends perpendicularly towards a base surface of the substrate and that surrounds the area of the substrate containing the functional circuit structure.