3D Trench Capacitor Coupling Across Dies for Higher Capacitance Density
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Solution Overview
Problem
Existing integrated passive devices (IPDs) face challenges in reducing size while maintaining high capacitance density, due to limitations in semiconductor manufacturing processes that affect the depth and aspect ratio of trench segments in 3D trench capacitors.
Innovation Solution
The implementation of a 3D trench capacitor structure that utilizes hybrid bonding or through substrate vias (TSVs) to electrically couple trench segments across multiple IC dies, allowing for increased capacitance density by summing the individual capacitances of 2D trench capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2D trench capacitor structures are used, then manufacturing process simplicity is maintained, but capacitance density is limited
Solution Approach 1:
The patent transitions from traditional 2D planar capacitor structures to 3D vertical trench capacitor structures. By extending the capacitor electrodes vertically into deep trenches etched into the semiconductor substrate, the effective capacitance area is dramatically increased without proportionally increasing the footprint area, thereby achieving high capacitance density while maintaining manufacturing feasibility through adapted fabrication processes
Solution Approach 2:
The patent implements stacked trench capacitor structures where multiple capacitor elements are vertically nested within the same footprint area. The trench segments are stacked in multiple layers with intermediate dielectric and conductive layers, allowing capacitances to be summed vertically while occupying minimal horizontal space, effectively nesting multiple functional elements within a compact volume
2Quantity of substance
If trench depth is increased to improve capacitance density, then capacitance increases, but manufacturing precision requirements worsen
Solution Approach 1:
The patent divides the deep trench capacitor structure into multiple discrete trench segments stacked vertically, each with manageable depth and aspect ratio. The trench segments are separated by intermediate dielectric layers and conductive coupling layers, allowing each segment to be formed with controlled dimensions while the overall structure achieves high capacitance through the cumulative effect of multiple segments
Solution Approach 2:
The patent optimizes the geometric parameters of the trench structure, including trench width, depth, and spacing, to achieve high capacitance density while maintaining manufacturable aspect ratios. By carefully controlling the dimensions of individual trench segments and the thickness of intermediate layers, the design balances capacitance performance with manufacturing precision requirements
3Quantity of substance
If multiple IC dies are bonded to increase capacitance density, then capacitance sums across dies, but device complexity increases
Solution Approach 1:
The patent combines multiple trench capacitor structures formed in different IC dies into a single integrated 3D trench capacitor system. Through wafer-level bonding techniques, the capacitors on separate dies are electrically connected in parallel, summing their capacitances while maintaining a compact integrated structure. This merging approach achieves high total capacitance without requiring a proportional increase in the number of discrete components
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.