3D TSV Stacking Architecture for Low-Resistance Die Interconnects
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Solution Overview
Problem
Existing integrated circuit packages face challenges in reducing contact resistance and signal delay due to multiple interfaces and longer communication paths when device dies are bonded through solder regions or metal pads.
Innovation Solution
The method involves joining package components through a die-attach film or fusion bonds and forming through-vias to directly connect conductive features, eliminating the need for solder regions and reducing interfaces, thereby minimizing contact resistance and signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device dies are bonded through solder regions or metal pads, then device dies can be connected electrically, but contact resistance and signal delay increase due to multiple interfaces and longer communication paths
Solution Approach 1:
The patent removes the intermediate solder regions and metal pads from the electrical connection path between device dies. By directly bonding conductive features (such as copper pillars or through-silicon vias) from one die to another, the harmful interfaces introduced by traditional bonding methods are eliminated, thereby reducing contact resistance and signal delay while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from planar bonding (where dies are connected through lateral solder joints) to vertical through-silicon connections. By routing conductive features through the thickness of the silicon substrate (TSVs), the electrical path moves to a different dimensional approach, creating shorter and more direct communication paths between stacked dies.
2Reliability
If multiple interfaces are used for bonding device dies, then electrical connections can be established, but contact resistance increases
Solution Approach 1:
The patent extracts and eliminates the intermediate bonding interfaces (solder layers, metal pads, and adhesive layers) that traditionally exist between device dies. By implementing direct conductive feature-to-conductive feature connections through the silicon substrate, the number of interfaces is reduced to minimal necessary layers, thereby significantly lowering contact resistance while maintaining reliable electrical connection.
3Reliability
If traditional bonding methods with solder regions are used, then device dies can be connected, but signal delay increases due to longer communication paths
Solution Approach 1:
The patent removes the lengthy signal path created by traditional solder-based bonding methods. By directly connecting conductive features through the silicon substrate without requiring lateral traversal through solder regions and metal pads, the communication path length is dramatically reduced, thereby minimizing signal delay while maintaining secure device connection.
Solution Approach 2:
The patent changes the signal transmission dimension from lateral (through solder joints at the die interface) to vertical (through the silicon substrate thickness). This dimensional shift creates a more direct and shorter communication path between corresponding conductive features on stacked dies, reducing signal propagation time and delay.
Data Source
AI summary
A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer. The redistribution line and the first through-via electrically connect a first conductive feature in the first wafer to a second conductive feature in the second wafer. An electrical connector is formed over the first wafer.